Capacitance Contribution of NIH/3T3 Cells Existing on and between Electrodes of an Impedance Biosensor.

In this study, an impedance biosensor capable of real-time monitoring of the growth and drug reactions using NIH/3T3 cells was fabricated through a semiconductor process. With the fabricated impedance biosensor, the cell growth and drug reaction states are monitored in real-time, showing the validness of the developed biosensor. By using the developed impedance biosensor, we have investigated the capacitance contribution of NIH/3T3 cells existing on electrodes and between electrodes.

Growth and Drug Interaction Monitoring of NIH 3T3 Cells by Image Analysis and Capacitive Biosensor.

Capacitive biosensors are manufactured on glass slides using the semiconductor process to monitor cell growth and cell-drug interactions in real time. Capacitance signals are continuously monitored for each 10 min interval during a 48 h period, with the variations of frequency from 1 kHz to 1 MHz. The capacitance values showed a gradual increase with the increase in NIH 3T3 cell numbers.

A 3D Printable Electroconductive Biocomposite Bioink Based on Silk Fibroin-Conjugated Graphene Oxide.

Reduced graphene oxide (rGO) has wide application as a nanofiller in the fabrication of electroconductive biocomposites due to its exceptional properties. However, the hydrophobicity and chemical stability of rGO limit its ability to be incorporated into precursor polymers for physical mixing during biocomposite fabrication. Moreover, until now, no suitable rGO-combining biomaterials that are stable, soluble, biocompatible, and 3D printable have been developed.

Highly Ordered Microscale-Pyramidal-Structure-Arrayed Silicon Membranes for Filter Applications.

Microscale-pyramidal-structure-arrayed patterned silicon membranes are manufactured using semiconductor processes and potassium hydroxide (KOH) etching techniques for filter applications. The silicon nitride on silicon on the insulator wafer functions as a masking layer, and the roughness of the silicon (100) plane strongly depends on the etching temperature and KOH concentration. To fabricate the membrane filter, a series of dry and wet etching using 45 wt% KOH solutions at the constant temperature of 70 °C was performed.

Hole Mobility Characteristics with Surface Roughness on Silicon-on-Insulator Substrate.

Hole mobility characteristics were investigated with surface roughness and silicon-on-insulator (SOI) thickness variations to investigate the influence of surface roughness to mobility. The root mean square roughness varied between 0.16, 0.

Scalability of Schottky barrier metal-oxide-semiconductor transistors.

In this paper, the general characteristics and the scalability of Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are introduced and reviewed. The most important factors, i.e.

Carrier Transport Properties of Bilayer Graphene Obtained via Hall Measurements.

The electron transport characteristics of bilayer graphene were investigated in terms of changes in the temperature from 2 to 300 K. The purpose of this study was a confirming the reported values5 of the carrier density and the mobility for using a ballistic quantum transport experiment. The mechanical exfoliation method was adopted to get the best quality of bilayer graphene and the number of layers of graphene was identified by the Raman spectra.

Silicide/Silicon Hetero-Junction Structure for Thermoelectric Applications.

We fabricated silicide/silicon hetero-junction structured thermoelectric device by CMOS process for the reduction of thermal conductivity with the scatterings of phonons at silicide/silicon interfaces. Electrical conductivities, Seebeck coefficients, power factors, and temperature differences are evaluated using the steady state analysis method. Platinum silicide/silicon multilayered structure showed an enhanced Seebeck coefficient and power factor characteristics, which was considered for p-leg element.

Effect of silicide/silicon hetero-junction structure on thermal conductivity and Seebeck coefficient.

We fabricated a thermoelectric device with a silicide/silicon laminated hetero-structure by using RF sputtering and rapid thermal annealing. The device was observed to have Ohmic characteristics by I-V measurement. The temperature differences and Seebeck coefficients of the proposed silicide/silicon laminated and bulk structure were measured.

The influence of ionized impurity scattering on the thermopower of Si nanowires.

The thermopower of Si nanowires was investigated on the basis of electronic transport theory, taking into account ionized impurity scattering as well as electron-phonon scattering. It was found that the enhancement of the Seebeck coefficient in nanowires arising from quantum confinement is unimportant due to the ionized impurity scattering associated with donor deactivation. Furthermore, because the electrical conductivity is degraded significantly as the nanowire size becomes smaller, despite the accompanying slightly enhanced Seebeck coefficient, the reduction of the nanowire size is not beneficial, at least for the thermopower of devices.

Seebeck coefficient characterization of highly doped n- and p-type silicon nanowires for thermoelectric device applications fabricated with top-down approach.

A silicon nanowire one-dimensional thermoelectric device is presented as a solution to enhance thermoelectric performance. A top-down process is adopted for the definition of 50 nm silicon nanowires (SiNWs) and the fabrication of the nano-structured thermoelectric devices on silicon on insulator (SOl) wafer. To measure the Seebeck coefficients of 50 nm width n- and p-type SiNWs, a thermoelectric test structure, containing SiNWs, micro-heaters and temperature sensors is fabricated.

Evaluation of Seebeck coefficients in n- and p-type silicon nanowires fabricated by complementary metal-oxide-semiconductor technology.

Silicon-based thermoelectric nanowires were fabricated by using complementary metal-oxide-semiconductor (CMOS) technology. 50 nm width n- and p-type silicon nanowires (SiNWs) were manufactured using a conventional photolithography method on 8 inch silicon wafer. For the evaluation of the Seebeck coefficients of the silicon nanowires, heater and temperature sensor embedded test patterns were fabricated.

Electronic transport of lateral PtSi/n/n+-Si Schottky diodes.

We investigated the transport properties of a lateral PtSi/n/n(+)-Si Schottky diode prepared on an n-type silicon-on-insulator (SOI) wafer with a special attention on the bipolar transport and the surface effect. With applying a back-gate bias changing from +18 V to -18 V, the unipolar transport behavior switched over to the bipolar one, where an enhanced surface recombination rate due to a high surface-to-volume ratio produced a current density approximately 3 x 10(3) A/cm2 for 2 V bias through a 40 nm-thick and 18 microm-long nanoribbon. The recombination time was estimated to be approximately 1 micros from independent CV measurements, which is much smaller value than that of a bulk.

Top-down processed silicon nanowires for thermoelectric applications.

50 nm wide n-type silicon nanowires have been manufactured by using a top-down process in order to investigate the thermoelectric properties of silicon nanowire. Nanowire test structures with platinum heaters and temperature sensors were fabricated. The extracted temperature coefficient of resistance (TCR) of the temperature sensors was 786.

Electrical characterization of n/p-type nickel silicide/silicon junctions by Sb segregation.

In this paper, n/p-type nickel-silicided Schottky diodes were fabricated by incorporating antimony atoms near the nickel silicide/Si junction interface and the electrical characteristics were studied through measurements and simulations. The effective Schottky barrier height (SBH) for electron, extracted from the thermionic emission model, drastically decreased from 0.68 to less than 0.

The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process.

Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured.