Role of a capping layer on the crystalline structure of Sn thin films grown at cryogenic temperatures on InSb substrates.

Metal deposition with cryogenic cooling is a common technique in the condensed matter community for producing ultra-thin epitaxial superconducting layers on semiconductors. However, a significant challenge arises when these films return to room temperature, as they tend to undergo dewetting. This issue can be mitigated by capping the films with an amorphous layer.

First-Principles Assessment of CdTe as a Tunnel Barrier at the α-Sn/InSb Interface.

Majorana zero modes, with prospective applications in topological quantum computing, are expected to arise in superconductor/semiconductor interfaces, such as β-Sn and InSb. However, proximity to the superconductor may also adversely affect the semiconductor's local properties. A tunnel barrier inserted at the interface could resolve this issue.

Andreev molecules in semiconductor nanowire double quantum dots.

Chains of quantum dots coupled to superconductors are promising for the realization of the Kitaev model of a topological superconductor. While individual superconducting quantum dots have been explored, control of longer chains requires understanding of interdot coupling. Here, double quantum dots are defined by gate voltages in indium antimonide nanowires.

Experimental phase diagram of zero-bias conductance peaks in superconductor/semiconductor nanowire devices.

Topological superconductivity is an exotic state of matter characterized by spinless p-wave Cooper pairing of electrons and by Majorana zero modes at the edges. The first signature of topological superconductivity is a robust zero-bias peak in tunneling conductance. We perform tunneling experiments on semiconductor nanowires (InSb) coupled to superconductors (NbTiN) and establish the zero-bias peak phase in the space of gate voltage and external magnetic field.

Dislocation-free axial InAs-on-GaAs nanowires on silicon.

We report on the growth of axial InAs-on-GaAs nanowire heterostructures on silicon by molecular beam epitaxy using 20 nm diameter Au catalysts. First, the growth parameters of the GaAs nanowire segment were optimized to achieve a pure wurtzite crystal structure. Then, we developed a two-step growth procedure to enhance the yield of vertical InAs-on-GaAs nanowires.

Growth and optical properties of axial hybrid III-V/silicon nanowires.

Hybrid silicon nanowires with an integrated light-emitting segment can significantly advance nanoelectronics and nanophotonics. They would combine transport and optical characteristics in a nanoscale device, which can operate in the fundamental single-electron and single-photon regime. III-V materials, such as direct bandgap gallium arsenide, are excellent candidates for such optical segments.

Bright single-photon sources in bottom-up tailored nanowires.

The ability to achieve near-unity light-extraction efficiency is necessary for a truly deterministic single-photon source. The most promising method to reach such high efficiencies is based on embedding single-photon emitters in tapered photonic waveguides defined by top-down etching techniques. However, light-extraction efficiencies in current top-down approaches are limited by fabrication imperfections and etching-induced defects.

Controlling the directional emission of light by periodic arrays of heterostructured semiconductor nanowires.

We demonstrate experimentally the directional emission of light by InAsP segments embedded in InP nanowires. The nanowires are arranged in a periodic array, forming a 2D photonic crystal slab. The directionality of the emission is interpreted in terms of the preferential decay of the photoexcited nanowires and the InAsP segments into Bloch modes of the periodic structure.

Crystal structure transfer in core/shell nanowires.

Structure engineering is an emerging tool to control opto-electronic properties of semiconductors. Recently, control of crystal structure and the formation of a twinning superlattice have been shown for III-V nanowires. This level of control has not been obtained for Si nanowires, the most relevant material for the semiconductor industry.

Generic nano-imprint process for fabrication of nanowire arrays.

A generic process has been developed to grow nearly defect-free arrays of (heterostructured) InP and GaP nanowires. Soft nano-imprint lithography has been used to pattern gold particle arrays on full 2 inch substrates. After lift-off organic residues remain on the surface, which induce the growth of additional undesired nanowires.