Analog Complementary Metal-Oxide-Semiconductor Integrate-and-Fire Neuron Circuit for Overflow Retaining in Hardware Spiking Neural Networks.

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining.

An Online Learning Method Using Spike-Timing Dependent Plasticity for Neuromorphic Systems.

In this study, we proposed an online learning method using spike-timing dependent plasticity (STDP) whose operation is analogous to gradient descent, the most successful learning algorithm for nonspiking artificial neural networks (ANNs). With a model of a 4-terminal synaptic transistor we previously reported, a single-layer neural network implemented on the cross-point array was simulated by MATLAB to train binary MNIST samples with gradient descent algorithm. In addition, a proposed pulse scheme based on STDP was used to train the same network by applying teaching pulses having positive and negative timing differences with respect to input pulses to the back gate of the synaptic transistors.

Analysis of Minority Carrier Lifetime Dependence on Dual Gate Feedback Field Effect Transistor.

In this paper, we investigated the dependence of minority carrier lifetime on dual gate FBFET. Generally, depending on the channel condition or trap density, the lifetime of minority carrier can be degraded. Since the potential barrier lowering through the accumulated carriers is essential for positive feedback, the deterioration of lifetime can make a critical influence on the operation of device.

Analysis of Hot Carrier Injection According to Gate Length.

In this paper, we analyze hot carrier injection (HCI) in an asymmetric dual gate structure with a charge storage layer. In a floating gate device, holes injected by HCI can move freely in the valence band, since the channel potential is constant. In case of charge trapping layer, however, holes are trapped only in the drain side where impact ionization occurs.

Simulation Program with Integrated Circuit Emphasis Compact Modeling of a Dual-Gate Positive-Feedback Field-Effect Transistor for Circuit Simulations.

In this work, we developed a SPICE compact model of a dual-gate positive-feedback field-effect transistor (FBFET) for circuit simulations by fitting the model to measurement results. We fabricated a FBFET and investigated the DC and transient characteristics. The fabricated FBFET has an extremely low sub-threshold slope and a low off current.

Polysilicon-Based Synaptic Transistor and Array Structure for Short/Long-Term Memory.

In this paper, we proposed and fabricated a polysilicon-based four-terminal synaptic transistor. The device has an asymmetric dual-gate structure. The top gate, which uses a thin SiO₂ layer as the gate dielectric, is the input terminal of the synaptic transistor, which receives spikes from pre-synaptic neurons.

Neuronal dynamics in HfO/AlO-based homeothermic synaptic memristors with low-power and homogeneous resistive switching.

We studied the pseudo-homeothermic synaptic behaviors by integrating complimentary metal-oxide-semiconductor-compatible materials (hafnium oxide, aluminum oxide, and silicon substrate). A wide range of temperatures, from 25 °C up to 145 °C, in neuronal dynamics was achieved owing to the homeothermic properties and the possibility of spike-induced synaptic behaviors was demonstrated, both presenting critical milestones for the use of emerging memristor-type neuromorphic computing systems in the near future. Biological synaptic behaviors, such as long-term potentiation, long-term depression, and spike-timing-dependent plasticity, are developed systematically, and comprehensive neural network analysis is used for temperature changes and to conform spike-induced neuronal dynamics, providing a new research regime of neurocomputing for potentially harsh environments to overcome the self-heating issue in neuromorphic chips.

Spiking Neural Networks with Unsupervised Learning Based on STDP Using Resistive Synaptic Devices and Analog CMOS Neuron Circuit.

We designed the CMOS analog integrate and fire (I&F) neuron circuit can drive resistive synaptic device. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, asymmetric negative and positive pulse generation part, a refractory part, and finally a back-propagation pulse generation part for learning of the synaptic devices. The resistive synaptic devices were fabricated using HfOx switching layer by atomic layer deposition (ALD).

Self-Boosted Tunnel Field-Effect Transistor Using Nitride Charge Trapping Layer for Low Supply Voltage Operation.

Tunneling field-effect transistors (TFETs) have been studied as a candidate for low-power device due to the remarkable subthreshold characteristics. However, digital circuits composed of TFET have significantly large propagation delay compared with the conventional MOSFET circuits because of small current drivability and large gate-to-drain capacitance. In this work, the electrical characteristics of the self-boosted TFETs with nitride charge trapping layer have been studied using TCAD simulations.

Neuromorphic System Based on CMOS Inverters and Si-Based Synaptic Device.

We developed an analog neuron circuit that can work with Si-based synaptic devices. N-channel and p-channel synaptic devices connected to current mirrors constitute the synaptic connection and integration parts to implement the excitation and inhibition mechanisms of biological neurons. The normal inverter controlling delay time and the modified inverter making negative pulse constitute the action-potential generation part to generate output action-potential.

Three-directional motion-compensation mask-based novel look-up table on graphics processing units for video-rate generation of digital holographic videos of three-dimensional scenes.

A three-directional motion-compensation mask-based novel look-up table method is proposed and implemented on graphics processing units (GPUs) for video-rate generation of digital holographic videos of three-dimensional (3D) scenes. Since the proposed method is designed to be well matched with the software and memory structures of GPUs, the number of compute-unified-device-architecture kernel function calls can be significantly reduced. This results in a great increase of the computational speed of the proposed method, allowing video-rate generation of the computer-generated hologram (CGH) patterns of 3D scenes.

Fast generation of video holograms of three-dimensional moving objects using a motion compensation-based novel look-up table.

A novel approach for fast generation of video holograms of three-dimensional (3-D) moving objects using a motion compensation-based novel-look-up-table (MC-N-LUT) method is proposed. Motion compensation has been widely employed in compression of conventional 2-D video data because of its ability to exploit high temporal correlation between successive video frames. Here, this concept of motion-compensation is firstly applied to the N-LUT based on its inherent property of shift-invariance.

Predictors of the change in the expression of emotional support within an online breast cancer support group: a longitudinal study.

Objectives: To explore how the expression of emotional support in an online breast cancer support group changes over time, and what factors predict this pattern of change.

Methods: We conducted growth curve modeling with data collected from 192 participants in an online breast cancer support group within the Comprehensive Health Enhancement Support System (CHESS) during a 24-week intervention period.

Results: Individual expression of emotional support tends to increase over time for the first 12 weeks of the intervention, but then decrease slightly with time after that.