Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks.

Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.

A 4.5 μW Miniaturized 3-Channel Wireless Intra-Cardiac Acquisition System.

This article presents a chip designed for wireless intra-cardiac monitoring systems. The design consists of a three-channel analog front-end, a pulse-width modulator featuring output-frequency offset and temperature calibration, and inductive data telemetry. By employing a resistance boosting technique in the instrumentation amplifier feedback, the pseudo-resistor exhibits lower non-linearity, leading to a total harmonic distortion of below 0.

NET-TEN: a silicon neuromorphic network for low-latency detection of seizures in local field potentials.

. Therapeutic intervention in neurological disorders still relies heavily on pharmacological solutions, while the treatment of patients with drug resistance remains an unresolved issue. This is particularly true for patients with epilepsy, 30% of whom are refractory to medications.

Mixed-Signal IC With Pulse Width Modulation Wireless Telemetry for Implantable Cardiac Pacemakers in 0.18-μm CMOS.

A low-power mixed-signal IC for implantable pacemakers is presented. The proposed system features three independent intracardiac signal readout channels with pulse-width-modulated outputs. Also, the proposed system is capable of measuring the amplitude and phase of the bioimpedance with pulse-width-modulated outputs for use in rate adaptive pacemakers.

A 1.55 μW Bio-Impedance Measurement System for Implantable Cardiac Pacemakers in 0.18 μm CMOS.

This paper presents an implantable bio-impedance measurement system for cardiac pacemakers. The fully integrated system features a low power analog front-end and pulse width modulated output. The bio-impedance readout benefits from voltage to time conversion to achieve a very low power consumption for wirelessly transmitting the data outside the body.