Dark-field optical fault inspection of ∼10 nm scale room-temperature silicon single-electron transistors.

Dark-field (DF) optical microscopy, combined with optical simulation based on modal diffraction theory for transverse electric polarized white light, is shown to provide non-invasive, sub-wavelength geometrical information for nanoscale etched device structures. Room temperature (RT) single electron transistors (SETs) in silicon, defined using etched ∼10 nm point-contacts (PCs) and in-plane side gates, are investigated to enable fabrication fault detection. Devices are inspected using scanning electron microscopy, bright-field (BF) and DF imaging.

Fast turnaround fabrication of silicon point-contact quantum-dot transistors using combined thermal scanning probe lithography and laser writing.

The fabrication of high-performance solid-state silicon quantum-devices requires high resolution patterning with minimal substrate damage. We have fabricated room temperature (RT) single-electron transistors (SETs) based on point-contact tunnel junctions using a hybrid lithography tool capable of both high resolution thermal scanning probe lithography and high throughput direct laser writing. The best focal z-position and the offset of the tip- and the laser-writing positions were determined in situ with the scanning probe.

Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors.

Single nanometre scale quantum dots (QDs) have significant potential for many 'beyond CMOS' nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation, <10 nm nanoscale point-contact channels are defined.

Single-electron and quantum confinement limits in length-scaled silicon nanowires.

Quantum-effects will play an important role in both future CMOS and 'beyond CMOS' technologies. By comparing single-electron transistors formed in un-patterned, uniform-width silicon nanowire (SiNW) devices with core widths from ∼5-40 nm, and gated lengths of 1 μm and ∼50 nm, we show conditions under which these effects become significant. Coulomb blockade drain-source current-voltage characteristics, and single-electron current oscillations with gate voltage have been observed at room temperature.