The future transistors.

The metal-oxide-semiconductor field-effect transistor (MOSFET), a core element of complementary metal-oxide-semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors.

Strong coupling between a photon and a hole spin in silicon.

Spins in semiconductor quantum dots constitute a promising platform for scalable quantum information processing. Coupling them strongly to the photonic modes of superconducting microwave resonators would enable fast non-demolition readout and long-range, on-chip connectivity, well beyond nearest-neighbour quantum interactions. Here we demonstrate strong coupling between a microwave photon in a superconducting resonator and a hole spin in a silicon-based double quantum dot issued from a foundry-compatible metal-oxide-semiconductor fabrication process.

Parametric Amplifiers Based on Quantum Dots.

Josephson parametric amplifiers (JPAs) approaching quantum-limited noise performance have been instrumental in enabling high fidelity readout of superconducting qubits and, recently, semiconductor quantum dots (QDs). We propose that the quantum capacitance arising in electronic two-level systems (the dual of Josephson inductance) can provide an alternative dissipationless nonlinear element for parametric amplification. We experimentally demonstrate phase-sensitive parametric amplification using a QD-reservoir electron transition in a CMOS nanowire split-gate transistor embedded in a 1.

Single-electron operations in a foundry-fabricated array of quantum dots.

Silicon quantum dots are attractive for the implementation of large spin-based quantum processors in part due to prospects of industrial foundry fabrication. However, the large effective mass associated with electrons in silicon traditionally limits single-electron operations to devices fabricated in customized academic clean rooms. Here, we demonstrate single-electron occupations in all four quantum dots of a 2 x 2 split-gate silicon device fabricated entirely by 300-mm-wafer foundry processes.

Single-Electron Operation of a Silicon-CMOS 2 × 2 Quantum Dot Array with Integrated Charge Sensing.

The advanced nanoscale integration available in CMOS technology provides a key motivation for its use in spin-based quantum computing applications. Initial demonstrations of quantum dot formation and spin blockade in CMOS foundry-compatible devices are encouraging, but results are yet to match the control of individual electrons demonstrated in university-fabricated multigate designs. We show that quantum dots formed in a CMOS nanowire device can be measured with a remote single electron transistor (SET) formed in an adjacent nanowire, via floating coupling gates.

Remote Capacitive Sensing in Two-Dimensional Quantum-Dot Arrays.

We investigate gate-induced quantum dots in silicon nanowire field-effect transistors fabricated using a foundry-compatible fully depleted silicon-on-insulator (FD-SOI) process. A series of split gates wrapped over the silicon nanowire naturally produces a 2 × bilinear array of quantum dots along a single nanowire. We begin by studying the capacitive coupling of quantum dots within such a 2 × 2 array and then show how such couplings can be extended across two parallel silicon nanowires coupled together by shared, electrically isolated, "floating" electrodes.

Gate-based high fidelity spin readout in a CMOS device.

The engineering of a compact qubit unit cell that embeds all quantum functionalities is mandatory for large-scale integration. In addition, these functionalities should present the lowest error rate possible to successfully implement quantum error correction protocols. Electron spins in silicon quantum dots are particularly promising because of their high control fidelity and their potential compatibility with complementary metal-oxide-semiconductor industrial platforms.

Electrical Spin Driving by g-Matrix Modulation in Spin-Orbit Qubits.

In a semiconductor spin qubit with sizable spin-orbit coupling, coherent spin rotations can be driven by a resonant gate-voltage modulation. Recently, we have exploited this opportunity in the experimental demonstration of a hole spin qubit in a silicon device. Here we investigate the underlying physical mechanisms by measuring the full angular dependence of the Rabi frequency, as well as the gate-voltage dependence and anisotropy of the hole g factor.

Level Spectrum and Charge Relaxation in a Silicon Double Quantum Dot Probed by Dual-Gate Reflectometry.

We report on dual-gate reflectometry in a metal-oxide-semiconductor double-gate silicon transistor operating at low temperature as a double quantum dot device. The reflectometry setup consists of two radio frequency resonators respectively connected to the two gate electrodes. By simultaneously measuring their dispersive responses, we obtain the complete charge stability diagram of the device.

Few-electron edge-state quantum dots in a silicon nanowire field-effect transistor.

We investigate the gate-induced onset of few-electron regime through the undoped channel of a silicon nanowire field-effect transistor. By combining low-temperature transport measurements and self-consistent calculations, we reveal the formation of one-dimensional conduction modes localized at the two upper edges of the channel. Charge traps in the gate dielectric cause electron localization along these edge modes, creating elongated quantum dots with characteristic lengths of ∼10 nm.

Few electron limit of n-type metal oxide semiconductor single electron transistors.

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning.