Ultra-High- Ferroelectric BaTiO Perovskite in the Gate Stack for Two-Dimensional WSe p-Type High-Performance Transistors.

The experimental demonstration of a p-type 2D WSe transistor with a ferroelectric perovskite BaTiO gate oxide is presented. The 30 nm thick BaTiO gate stack shows a robust ferroelectric hysteresis with a remanent polarization of 20 μC/cm and further enables a capacitance equivalent thickness of 0.5 nm in the hybrid WSe/BaTiO stack due to its high dielectric constant of 323.

Process integration and future outlook of 2D transistors.

The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the recent progress in the fabrication of complementary metal-oxide-semiconductor (CMOS) devices based on stacked 2D TMD nanoribbons and specifically highlight issues that still need to be resolved by the 2D community in five crucial research areas: contacts, channel growth, gate oxide, variability, and doping. While 2D TMD transistors have great potential, more research is needed to understand the physical interactions of 2D materials at the atomic scale.

Toward attojoule switching energy in logic transistors.

Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling-the decrease of component sizes-with each new process node continues today, albeit at a slower pace compared with historical rates of scaling.