An Event-Based Neural Compressive Telemetry With >11× Loss-Less Data Reduction for High-Bandwidth Intracortical Brain Computer Interfaces.

Intracortical brain-computer interfaces offer superior spatial and temporal resolutions, but face challenges as the increasing number of recording channels introduces high amounts of data to be transferred. This requires power-hungry data serialization and telemetry, leading to potential tissue damage risks. To address this challenge, this paper introduces an event-based neural compressive telemetry (NCT) consisting of 8 channel-rotating Δ-ADCs, an event-driven serializer supporting a proposed ternary address event representation protocol, and an event-based LVDS driver.

A Spatially Diverse 2TX-3RX Galvanic-Coupled Transdural Telemetry for Tether-Less Distributed Brain-Computer Interfaces.

A near-field galvanic coupled transdural telemetry ASICs for intracortical brain-computer interfaces is presented. The proposed design features a two channels transmitter and three channels receiver (2TX-3RX) topology, which introduces spatial diversity to effectively mitigate misalignments (both lateral and rotational) between the brain and the skull and recovers the path loss by 13 dB when the RX is in the worst-case blind spot. This spatial diversity also allows the presented telemetry to support the spatial division multiplexing required for a high-capacity multi-implant distributed network.

A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application.

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.