Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform.

This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs.

A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers.

Global navigation satellite system (GNSS) technology is evolving at a rapid pace. The rapid advancement demands rapid prototyping tools to conduct research on new and innovative signals and systems. However, researchers need to deal with the increasing complexity and integration level of GNSS integrated circuits (IC), resulting in limited access to modify or inspect any internal aspect of the receiver.