Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement.

Carbon nanotube circuit integration up to sub-20 nm channel lengths.

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size).

VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, as-made carbon nanotube field effect transistors (CNFETs) are p-type in ambient, and a consistent and reproducible n-type carbon nanotube (CNT) doping technique has yet to be realized. In addition, for very large scale integration (VLSI) of CNT transistors, it is imperative to use a solid-state method that can be applied on the wafer scale.

Atomic layer deposition of high-k dielectrics on single-walled carbon nanotubes: a Raman study.

Single-wall carbon nanotubes (SWCNTs) have great potential to become the channel material for future high-speed transistor technology. However, to realize a carbon nanotube field effect transistor (CNTFET) with excellent gate control, the high-k dielectrics between the CNT and the metal gate must have superb electrical properties and extremely high uniformity. Thus it is essential to understand the interactions between high-k materials and the SWCNTs to effectively control the transistor characteristics.

Wafer-scale fabrication and characterization of thin-film transistors with polythiophene-sorted semiconducting carbon nanotube networks.

Semiconducting single-walled carbon nanotubes (SWCNTs) have great potential of becoming the channel material for future thin-film transistor technology. However, an effective sorting technique is needed to obtain high-quality semiconducting SWCNTs for optimal device performance. In our previous work, we reported a dispersion technique for semiconducting SWCNTs that relies on regioregular poly(3-dodecylthiophene) (rr-P3DDT) to form hybrid nanostructures.