The CeO-based memristor has attracted significant attention due to its intrinsic resistive switching (RS) properties, large on/off ratio, and great plasticity, making it a promising candidate for artificial synapses. However, significant challenges such as high power consumption and poor device reliability hinder its broad application in neuromorphic microchips. To tackle these issues, in this work, we design a novel bilayer (BL) memristor by integrating a CeO-based memristor with a Co-CeO vertically aligned nanocomposite (VAN) layer and compare it with the single layer (SL) memristor.
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