Geometric control of diffusing elements on InAs semiconductor surfaces via metal contacts.

Local geometric control of basic synthesis parameters, such as elemental composition, is important for bottom-up synthesis and top-down device definition on-chip but remains a significant challenge. Here, we propose to use lithographically defined metal stacks for regulating the surface concentrations of freely diffusing synthesis elements on compound semiconductors. This is demonstrated by geometric control of Indium droplet formation on Indium Arsenide surfaces, an important consequence of incongruent evaporation.

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor.

Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications.

Effects of Interface Oxidation on Noise Properties and Performance in III-V Vertical Nanowire Memristors.

Memristors implemented as resistive random-access memories (RRAMs) owing to their low power consumption, scalability, and speed are promising candidates for in-memory computing and neuromorphic applications. Moreover, a vertical 3D implementation of RRAMs enables high-density crossbar arrays at a minimal footprint. Co-integrated III-V vertical gate-all-around MOSFET selectors in a one-transistor-one-resistor (1T1R) configuration have recently been demonstrated where an interlayer (IL)-oxide has been shown to enable high RRAM endurance needed for applications like machine learning.

Sensing single domains and individual defects in scaled ferroelectrics.

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors.

Ferroelectric-Antiferroelectric Transition of Hf Zr O on Indium Arsenide with Enhanced Ferroelectric Characteristics for HfZrO.

The ferroelectric (FE)-antiferroelectric (AFE) transition in Hf Zr O (HZO) is for the first time shown in a metal-ferroelectric-semiconductor (MFS) stack based on the III-V material InAs. As InAs displays excellent electron mobility and a narrow band gap, the integration of ferroelectric thin films for nonvolatile operations is highly relevant for future electronic devices and motivates further research on ferroelectric integration. When increasing the Zr fraction from 0.

Correction: Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction.

Correction for 'Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction' by Dmitry Dzhigaev , , 2020, , 14487-14493, DOI: 10.1039/D0NR02260H.

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si.

Sb-based semiconductors are critical p-channel materials for III-V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared.

Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance.

Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel material in metal oxide semiconductor field effect transistors (MOSFETs) due to attractive carrier transport properties. However, for improved performance in terms of current density as well as contact resistance, adequate characterization techniques for resolving doping distribution within thin vertical nanowires are required. We present a novel method of axially probing the doping profile by systematically changing the gate position, at a constant gate length of 50 nm and a channel diameter of 12 nm, along a vertical nanowire MOSFET and utilizing the variations in threshold voltage shift (∼100 mV).

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing.

GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance () by 50% among 28 devices and achieved 70Smat = -0.5 V in a device with 200 nm gate length.

Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction.

Semiconductor nanowires in wrapped, gate-all-around transistor geometry are highly favorable for future electronics. The advanced nanodevice processing results in strain due to the deposited dielectric and metal layers surrounding the nanowires, significantly affecting their performance. Therefore, non-destructive nanoscale characterization of complete devices is of utmost importance due to the small feature sizes and three-dimensional buried structure.

Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth.

Here we present a method to control the size of the openings in hexagonally organized BCP thin films of poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) by using surface reconstruction. The surface reconstruction is based on selective swelling of the P4VP block in ethanol, and its extraction to the surface of the film, resulting in pores upon drying. We found that the BCP pore diameter increases with ethanol immersion temperature.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state.

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors.

In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors (TFETs) to study the influence of source doping on their performance. Overall, the doping level impacts both the off-state and on-state performance of these devices. Separation of the doping from the heterostructure improved the subthreshold swing of the devices.

Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si.

III-V compound semiconductors offer a path to continue Moore's law due to their excellent electron transport properties. One major challenge, integrating III-V's on Si, can be addressed by using vapor-liquid-solid grown vertical nanowires. InAs is an attractive material due to its superior mobility, although InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) typically suffer from band-to-band tunneling caused by its narrow band gap, which increases the off-current and therefore the power consumption.

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade.

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InGaAsSb/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction.

Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions.

In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in Dit as compared to planar references.

Low Leakage-Current InAsSb Nanowire Photodetectors on Silicon.

Axially doped p-i-n InAs0.93Sb0.07 nanowire arrays have been grown on Si substrates and fabricated into photodetectors for shortwave infrared detection.

III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.

III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I(on)/I(off) ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.

Hard X-ray detection using a single 100 nm diameter nanowire.

Submicron sized sensors could allow higher resolution in X-ray imaging and diffraction measurements, which are ubiquitous for materials science and medicine. We present electrical measurements of a single 100 nm diameter InP nanowire transistor exposed to hard X-rays. The X-ray induced conductance is over 5 orders of magnitude larger than expected from reported data for X-ray absorption and carrier lifetimes.

InAs nanowire MOSFETs in three-transistor configurations: single balanced RF down-conversion mixers.

Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversion mixer circuits, fabricated using vertically aligned InAs nanowire devices on Si. A thin, highly doped InAs buffer layer has been introduced to reduce the access resistance and serve as a bottom electrode.

Electrical properties of GaSb/InAsSb core/shell nanowires.

Temperature dependent electronic properties of GaSb/InAsSb core/shell and GaSb nanowires have been studied. Results from two-probe and four-probe measurements are compared to distinguish between extrinsic (contact-related) and intrinsic (nanowire) properties. It is found that a thin (2-3 nm) InAsSb shell allows low barrier charge carrier injection to the GaSb core, and that the presence of the shell also improves intrinsic nanowire mobility and conductance in comparison to bare GaSb nanowires.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al.

Synthesis and properties of antimonide nanowires.

Antimonide semiconductors are suitable for low-power electronics and long-wavelength optoelectronic applications. In recent years research on antimonide nanowires has become a rapidly growing field, and nano-materials have promising applications in fundamental physics research, for tunnel field-effect transistors, and long-wavelength detectors. In this review, we give an overview of the field of antimonide nanowires, beginning with a description of the synthesis of these nano-materials.