Publications by authors named "L Feigl"

Here we report on the non-uniform shell growth of InGaAs on the GaAs nanowire (NW) core by molecular beam epitaxy (MBE). The growth was realized on pre-patterned silicon substrates with the pitch size () ranging from 0.1 μm to 10 μm.

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Misfit strain in core-shell nanowires can be elastically released by nanowire bending in case of asymmetric shell growth around the nanowire core. In this work, we investigate the bending of GaAs nanowires during the asymmetric overgrowth by an InGaAs shell caused by avoiding substrate rotation. We observe that the nanowire bending direction depends on the nature of the substrate's oxide layer, demonstrated by Si substrates covered by native and thermal oxide layers.

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Design of novel nanowire (NW) based semiconductor devices requires deep understanding and technological control of NW growth. Therefore, quantitative feedback over the structure evolution of the NW ensemble during growth is highly desirable. We analyse and compare the methodical potential of reflection high-energy electron diffraction (RHEED) and X-ray diffraction reciprocal space imaging (XRD) for in situ growth characterization during molecular-beam epitaxy (MBE).

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We present an approach for quantitative evaluation of time-resolved reflection high-energy electron diffraction (RHEED) intensity patterns measured during the growth of vertical, free-standing nanowires (NWs). The approach considers shadowing due to attenuation by absorption and extinction within the individual nanowires and estimates the time dependence of its influence on the RHEED signal of the nanowire ensemble as a function of instrumental RHEED parameters and the growth dynamics averaged over the nanowire ensemble. The developed RHEED simulation model takes into account the nanowire structure evolution related to essential growth aspects, such as axial growth, radial growth with tapering and facet growth, as well as so-called parasitic intergrowth on the substrate.

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The growth of regular arrays of uniform III-V semiconductor nanowires is a crucial step on the route toward their application-relevant large-scale integration onto the Si platform. To this end, not only does optimal vertical yield, length, and diameter uniformity have to be engineered, but also, control over the nanowire crystal structure has to be achieved. Depending on the particular application, nanowire arrays with varying area density are required for optimal device efficiency.

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