Weighted-Sum Operation of Three-Terminal Synapse Transistors in Array Configuration Using Spin-Coated Li-Doped ZrO Electrolyte Gate Insulator.

Artificial synapses with ideal functionalities are essential in hardware neural networks to allow for energy-efficient analog computing. Electrolyte-gated transistors (EGTs) are promising candidates for artificial synaptic devices due to their low voltage operations supported by large specific capacitances of electrolyte gate insulators (EGIs). We investigated the synapse transistor employing an In-Ga-Zn-O channel and a Li-doped ZrO (LZO) EGI so as to improve the short-term plasticity (STP) and long-term potentiation (LTP).

Improvement in current drivability and stability in nanoscale vertical channel thin-film transistors via band-gap engineering in In-Ga-Zn-O bilayer channel configuration.

Vertical channel thin film transistors (VTFTs) have been expected to be exploited as one of the promising three-dimensional devices demanding a higher integration density owing to their structural advantages such as small device footprints. However, the VTFTs have suffered from the back-channel effects induced by the pattering process of vertical sidewalls, which critically deteriorate the device reliability. Therefore, to reduce the detrimental back-channel effects has been one of the most urgent issues for enhancing the device performance of VTFTs.

Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subμm Channel Lengths.

Roles of oxygen interstitial defects located in the In-Ga-Zn-O (IGZO) thin films prepared by atomic layer deposition were investigated with controlling the cationic compositions and gate-stack process conditions. It was found from the spectroscopic ellipsometry analysis that the excess oxygens increased with increasing the In contents within the IGZO channels. While the device using the IGZO channel with an In/Ga ratio of 0.

Implementation of oxide vertical channel TFTs with sub-150 nm channel length using atomic-layer deposited IGZO active and HfOgate insulator.

We fabricated vertical channel thin film transistors (VTFTs) with a channel length of 130 nm using an ALD In-Ga-Zn-O (IGZO) active channel and high-k HfOgate insulator layers. Solution-processed SiOthin film, which exhibited an etch selectivity as high as 4.2 to drain electrode of indium-tin oxide, was introduced as a spacer material.

Comparative studies on vertical-channel charge-trap memory thin-film transistors using In-Ga-Zn-O active channels deposited by sputtering and atomic layer depositions.

Vertical-channel charge-trap memory thin film-transistors (V-CTM TFTs) using oxide semiconductors were fabricated and characterized, in which In-Ga-Zn-O (IGZO) channels were prepared by sputtering and atomic-layer deposition (ALD) methods to elucidate the effects of deposition process. The vertical-channel gate stack of the fabricated device was verified to be well implemented on the vertical sidewall of the spacer patterns due to excellent step-coverage and self-limiting mechanisms of ALD process. The V-CTM TFTs using ALD-IGZO channel exhibited a wide memory window (MW) of 15.