Effect of interface defects on electrical characteristics of a-ITGZO TFTs under bottom, top, and dual gatings.

Here, we investigate the effects of interface defects on the electrical characteristics of amorphous indium-tin-gallium-zinc oxide (a-ITGZO) thin-film transistors (TFTs) utilizing bottom, top, and dual gatings. The field-effect mobility (27.3 cm/V∙s) and subthreshold swing (222 mV/decade) under a dual gating is substantially better than those under top (12.

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism.

This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0A, and a retention time of around 1 s without any external bias.

Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors.

In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator exhibited uniform probability distributions of 51.

Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels.

In this study, we investigate the gate-bias stability of triple-gated feedback field-effect transistors (FBFETs) with Si nanosheet channels. The subthreshold swing (SS) of FBFETs increases from 0.3 mV decto 60 and 80 mV decin- and-channel modes, respectively, when a positive bias stress (PBS) is applied for 1000 s.

Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors.

In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of -200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from -1.

Binary and ternary logic-in-memory using nanosheet feedback field-effect transistors with triple-gated structure.

In this study, we demonstrate binary and ternary logic-in-memory (LIM) operations of inverters and NAND and NOR gates comprising nanosheet (NS) feedback field-effect transistors (FBFETs) with a triple-gated structure. The NS FBFETs are reconfigured in p- or n-channel modes depending on the polarity of the gate bias voltage and exhibit steep switching characteristics with an extremely low subthreshold swing of 1.08 mV dec and a high ON/OFF current ratio of approximately 10.

Binarized neural network of diode array with high concordance to vector-matrix multiplication.

In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector-matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p-n-p-n device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 10). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.

Read Operation Mechanism of Feedback Field-Effect Transistors with Quasi-Nonvolatile Memory States.

In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, generating the memory state "State 1 (State 0)". Read pulses of 40 ns read these states with a retention time of 3 s, and the potential barrier formation and carrier accumulation were influenced by these read pulses.

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors.

Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated.

Anti‑tumor properties of FoxO1 in YD‑9 oral squamous cell carcinoma cells.

Oral squamous cell carcinoma (OSCC) is a tumor with a poor prognosis and a high recurrence rate. Despite its high annual incidence worldwide, appropriate therapeutic strategies have not yet been developed. Consequently, the 5‑year survival rate for OSCC is low when advanced stages or recurrence is diagnosed.

Universal logic-in-memory cell enabling all basic Boolean algebra logic.

Among the promising approaches for implementing high-performance computing, reconfigurable logic gates and logic-in-memory (LIM) approaches have been drawing increased research attention. These allow for improved functional scaling of a chip, owing to the improved functionality per unit area. Although numerous studies have been conducted independently for either reconfigurable logic or LIM units, attempts to construct a hybrid structure based on reconfigurable logic and LIM units remain relatively rare.

New ternary inverter with memory function using silicon feedback field-effect transistors.

In this study, we present a fully complementary metal-oxide-semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a positive feedback loop by carrier accumulation in their channels, which allows to achieve excellent memory characteristics with extremely low subthreshold swings. This hybrid operation of the switching and memory functions enables FBFETs to implement memory operation in a conventional CMOS logic scheme.

Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors.

In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode technology computer-aided design simulation. The DG FBFETs can be reconfigured to n- or p-channel modes, and these modes exhibit an on/off current ratio of ~ 10 and a subthreshold swing (SS) of ~ 0.4 mV/dec.

Reconfiguration of operation modes in silicon nanowire field-effect transistors by electrostatic virtual doping.

In this study, we perform reconfigurable n- and p-channel operations of a tri-top-gate field-effect transistor (FET) made of a p-i-nsilicon nanowire (SiNW). In the reconfigurable FET (RFET), two polarity gates and one control gate induce virtual electrostatic doping in the SiNW channel. The polarity gates are electrically connected to each other and program the channel type, while the control gate modulates the flow of charge carriers in the SiNW channel.

Design and Simulation of Logic-In-Memory Inverter Based on a Silicon Nanowire Feedback Field-Effect Transistor.

In this paper, we propose a logic-in-memory (LIM) inverter comprising a silicon nanowire (SiNW) n-channel feedback field-effect transistor (n-FBFET) and a SiNW p-channel metal oxide semiconductor field-effect transistor (p-MOSFET). The hybrid logic and memory operations of the LIM inverter were investigated by mixed-mode technology computer-aided design simulations. Our LIM inverter exhibited a high voltage gain of 296.

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors.

The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations.

Performance Prediction of Hybrid Energy Harvesting Devices Using Machine Learning.

In this study, we used machine learning to predict the output power of hybrid energy devices (HEDs) comprising photovoltaic cells (PVCs) and thermoelectric generators (TEGs). For the five types of HEDs, eight different machine learning models were trained and tested with experimental data; the HED each had different interface materials between the PVCs and the TEGs. An artificial neural network (ANN) model, which is the most appropriate model, predicted the correlation between HED performance and interface material properties.

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges.

In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I-V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.

One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors.

In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 10 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.

Integrate-and-Fire Neuron Circuit Without External Bias Voltages.

In this study, we propose an integrate-and-fire (I&F) neuron circuit using a - diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.

Thermoelectric Characteristics of Ultrathin Ag₂Se Films with Durability Against Mechanical Stress.

In this study, we investigated thermoelectric materials with durability against mechanical stress using Ag₂Se nanoparticle (NP) thin films and colorless polyimide (CPI) substrates. Ag₂Se NP thin films and CPI substrates were produced by spin-coating, and their thicknesses were 40 nm and 15 m, respectively. A bendable thermoelectric film with a channel length of 40 m and a channel area of 1.

Effect of Electrode Materials on the Electrical Characteristics of Amorphous Indium-Tin-Gallium-Zinc Oxide Thin-Film Transistors.

In this study, we investigated the effect of electrode materials on the electrical characteristics of coplanar top-gate a-ITGZO thin-film transistors, in which the gate, source, and drain electrodes were made of the same metal, Ti or Al. The field-effect mobilities of the a-ITGZO thin-film transistors with Ti and Al electrodes were 35.2 and 20.

Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors.

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory.

Performance of Hybrid Energy Devices Consisting of Photovoltaic Cells and Thermoelectric Generators.

The aim of our study on hybrid energy devices (HEDs) is to find out the prerequisites for enhancing the performance of the HEDs using solar energy. In this work, first of all, the performance of the HEDs composed of photovoltaic cells (PVCs) and thermoelectric generators (TEGs) is analyzed, and then the contribution of three different interfaces between the PVC and TEG components to HED performance is assessed under solar irradiance from 200 to 1000 W/m. The significant result of the analysis emphasizes that the performance of HEDs is enhanced when short-circuit current in HEDs is comparable with the PVCs and the thermoelectric voltage generated by the TEG is large.

Effect of carbon black addition on thermal stability and capacitive performances of supercapacitors.

In this study, we propose a simple way to improve thermal stability of solid-state supercapacitors (SCs) by adding carbon black (CB) into reduced graphene oxide (rGO) electrodes. The CB used as a heat-resistant additive contributes to stable operation of the rGO-CB SC even after 1000 charge/discharge cycles at 90 °C. In the case of the rGO SC without CB, it fails after the 166th cycles at 90 °C.