A Study on the Development of Real-Time Chamber Contamination Diagnosis Sensors.

Plasma processes are critical for achieving precise device fabrication in semiconductor manufacturing. However, polymer accumulation during processes like plasma etching can cause chamber contamination, adversely affecting plasma characteristics and process stability. This study focused on developing a real-time sensor system for diagnosing chamber contamination by quantitatively monitoring polymer accumulation.

Clean SiO atomic layer etching based on physisorption of high boiling point perfluorocarbon.

This study aimed to evaluate the SiO atomic layer etching (ALE) process that is selective to SiN based on the physisorption of high boiling point perfluorocarbons (HBP PFCs; CF, CF, CF, and CF have boiling points above room temperature). The lowering of the substrate temperature from 20 °C to -20 °C not only increased SiO etch depth per cycle (EPC) but also increased etch selectivity of SiO/SiN to near infinity. Due to the differences in fluorocarbon adsorption at a temperature during the physisorption depending on boiling points of PFCs, the desorption time and ion bombardment energy during the desorption step needed to be optimized, and higher ion bombardment energy and longer desorption time were required for higher HBP PFCs.

Atomic Layer Etching Using a Novel Radical Generation Module.

To fabricate miniature semiconductors of 10 nm or less, various process technologies have reached their physical limits, and new process technologies for miniaturization are required. In the etching process, problems such as surface damage and profile distortion have been reported during etching using conventional plasma. Therefore, several studies have reported novel etching techniques such as atomic layer etching (ALE).

Etch characteristics of Si and TiO nanostructures using pulse biased inductively coupled plasmas.

The etch characteristics of Si and TiO nanostructures for optical devices were investigated using pulse biased inductively coupled plasmas (ICP) with SF/CF/Ar and BCl/Ar, respectively, and the results were compared with those etched using continuous wave (CW) biased ICP. By using pulse biasing compared to CW biasing in the etching of the line/pillar nanostructures with various aspect ratios, there was a reduction of the aspect ratio dependent etching (ARDE) and therefore, uniform etch depths for nanostructures with different pattern widths, as well as the improvement of the etch profiles without any notching, were obtained not only for silicon nanostructures but also for TiO nanostructures. The investigation has determined that the improvement of etch profiles and reduced ARDE effect when using pulse biasing are related to the decreased surface charging caused by neutralization of the surface and the improved radical adsorption (or etch byproduct removal) on the etched surfaces during the pulse-off period for pulse biasing compared to CW biasing.

Improvement of a block co-polymer (PS-b-PMMA)-masked silicon etch profile using a neutral beam.

Bottom-up block copolymer (BCP) lithography mediated by self-assembly of polystyrene (PS)/poly-methyl methacrylate (PMMA) is widely used as an alternative patterning method for various deep nanoscale devices, such as optical devices and transistors, replacing conventional top-down photolithography. However, the nanoscale BCP mask features formed on the substrates after direct self-assembly of BCP tend to be easily damaged during exposure to the following plasma processing. In this study, silicon masked with a nanoscale BCP mask (PS) was etched by irradiating with a Cl2/Ar neutral beam in addition to a Cl2/Ar ion beam, and the effect of a Cl2/Ar neutral beam instead of a Cl2/Ar ion beam on damage to the PS mask and the silicon etch characteristics of nanodevices was investigated.

Controlled Layer-by-Layer Etching of MoS₂.

Two-dimensional (2D) metal dichalcogenides like molybdenum disulfide (MoS2) may provide a pathway to high-mobility channel materials that are needed for beyond-complementary metal-oxide-semiconductor (CMOS) devices. Controlling the thickness of these materials at the atomic level will be a key factor in the future development of MoS2 devices. In this study, we propose a layer-by-layer removal of MoS2 using the atomic layer etching (ALET) that is composed of the cyclic processing of chlorine (Cl)-radical adsorption and argon (Ar)(+) ion-beam desorption.