The sodium ion-assisted memory behaviour of a silicon nanowire partial composite field-effect transistor.

A partial composite consisting of rough silicon nanowires and a polymer dielectric layer with sufficient Na(+) ions was used to create a field-effect transistor based memory device. Addition of Na(+) ions helped compensate for water molecule trapped charges leading to narrow hysteresis characteristics and stable memory retention stability of the resulting device.

White light emission from heterojunction diodes based on surface-oxidized porous Si nanowire arrays and amorphous In-Ga-Zn-O capping.

A novel heterojunction white light emitting diode (LED) structure based on an array of vertically aligned surface-passivated p-type porous Si nanowires (PSiNWs) with n-type amorphous In-Ga-Zn-O (a-IGZO) capping is introduced. PSiNWs were initially synthesized by electroless etching of p-type Si (100) wafers assisted by Ag nanoparticle catalysts and then surface-passivated by thermal oxidation. The nanowires synthesized by metal-assisted electroless etching were found to have longitudinally varying nanoporous morphologies due to differences in the duration of exposure to etching environment.

A route for modulating the diameter of cylindrical silicon nanowires by using thermal self-ordering silver nanoparticles.

For the synthesis of uniform sub-80-nm silicon nanowires (Si NWs), we introduce a metal-assisted chemical etching (MCE)-based facile and high-yield route, employing simple thermal annealing and vacuum deposition processes. Under rapid thermal annealing, an ultrathin silver (Ag) film on a Si substrate is self-organized into Ag nanoparticles (NPs), which are used for making Si nanoholes through a short MCE process. After sputter deposition of Au (10 nm)/Ag (20 nm) on the caved Si substrate with nanoholes, a nanomesh is obtained.

Effects of solution temperature on solution-processed high-performance metal oxide thin-film transistors.

Herein, we report a novel and easy strategy for fabricating solution-processed metal oxide thin-film transistors by controlling the dielectric constant of H2O through manipulation of the metal precursor solution temperature. As a result, indium zinc oxide (IZO) thin-film transistors (TFTs) fabricated from IZO solution at 4 °C can be operated after annealing at low temperatures (∼250 °C). In contrast, IZO TFTs fabricated from IZO solutions at 25 and 60 °C must be annealed at 275 and 300 °C, respectively.

Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.

A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.

One-dimensional semiconductor nanostructure based thin-film partial composite formed by transfer implantation for high-performance flexible and printable electronics at low temperature.

Having high bending stability and effective gate coupling, the one-dimensional semiconductor nanostructures (ODSNs)-based thin-film partial composite was demonstrated, and its feasibility was confirmed through fabricating the Si NW thin-film partial composite on the poly(4-vinylphenol) (PVP) layer, obtaining uniform and high-performance flexible field-effect transistors (FETs). With the thin-film partial composite optimized by controlling the key steps consisting of the two-dimensional random dispersion on the hydrophilic substrate of ODSNs and the pressure-induced transfer implantation of them into the uncured thin dielectric polymer layer, the multinanowire (NW) FET devices were simply fabricated. As the NW density increases, the on-current of NW FETs increases linearly, implying that uniform NW distribution can be obtained with random directions over the entire region of the substrate despite the simplicity of the drop-casting method.

Programmable direct-printing nanowire electronic components.

In order for recently developed advanced nanowire (NW) devices(1-5) to be produced on a large scale, high integration of the separately fabricated nanoscale devices into intentionally organized systems is indispensible. We suggest a unique fabrication route for semiconductor NW electronics. This route provides a high yield and a large degree of freedom positioning the device on the substrate.