Formation of metal and dielectric liners using a solution process for deep trench capacitors.

We demonstrated the feasibility of metal and dielectric liners using a solution process for deep trench capacitor application. The deep Si trench via with size of 10.3 microm and depth of 71 microm were fabricated by Bosch process in deep reactive ion etch (DRIE) system.

The effect of thermal annealing on pentacene thin film transistor with micro contact printing.

We used micro contact printing (micro-CP) to fabricate inverted coplanar pentacene thin film transistors (TFTs) with 1-microm channels. The patterning of micro-scale source/drain electrodes without etch process was successfully achieved using Polydimethylsiloxane (PDMS) elastomer stamp. We used the Ag nano particle ink as an electrode material, and the sheet resistance and surface roughness of the Ag electrodes were effectively reduced with the 2-step thermal annealing on a hotplate, which improved the mobility, the on-off ratio, and the subthreshold slope (SS) of the pentacene TFTs.

Sub-30 nm gate template fabrication for nanoimprint lithography using spacer patterning technology.

In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness.

Sub-50 nm template fabrications for nanoimprint lithography using hydrogen silsesquioxane and silicon nitride.

The sub-50 nm templates are successfully fabricated using hydrogen silsesquioxane (HSQ) and silicon nitride on silicon substrate. The HSQ template is directly patterned by e-beam direct writing. The cured HSQ pattern is used for the template of nanoimprint process.