Processes to enable hysteresis-free operation of ultrathin ALD Te p-channel field-effect transistors.

Recently, tellurium (Te) has been proposed as a promising p-type material; however, even the state-of-the-art results couldn't overcome the critical roadblocks for its practical applications, such as large - hysteresis and high off-state leakage current. We developed a novel Te atomic layer deposition (ALD) process combined with a TeO seed layer and AlO passivation to detour the limitations of p-type Te semiconducting materials. Also, we have identified the origins of high hysteresis and off current using the 77 K operation study and passivation process optimization.

Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process.

A p-type ternary logic device with a stack-channel structure is demonstrated using an organic p-type semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). A photolithography-based patterning process is developed to fabricate scaled electronic devices with complex organic semiconductor channel structures. Two layers of thin DNTT with a separation layer are fabricated via the low-temperature deposition process, and for the first time, p-type ternary logic switching characteristics exhibiting zero differential conductance in the intermediate current state are demonstrated.

Dual-channel P-type ternary DNTT-graphene barristor.

P-type ternary switch devices are crucial elements for the practical implementation of complementary ternary circuits. This report demonstrates a p-type ternary device showing three distinct electrical output states with controllable threshold voltage values using a dual-channel dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]-thiophene-graphene barristor structure. To obtain transfer characteristics with distinctively separated ternary states, novel structures called contact-resistive and contact-doping layers were developed.

Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits.

Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼10) and adjustable operating range characteristics was successfully demonstrated using a ZnO and dinaphtho[2,3-:2',3'-]thieno[3,2-]thiophene heterojunction structure. The entire device integration was completed at a low thermal budget of less than 200 °C, which makes this AAS device compatible with monolithic 3D integration.

Channel Defect Profiling and Passivation for ZnO Thin-Film Transistors.

The electrical characteristics of Zinc oxide (ZnO) thin-film transistors are analyzed to apprehend the effects of oxygen vacancies after vacuum treatment. The energy level of the oxygen vacancies was found to be located near the conduction band of ZnO, which contributed to the increase in drain current (I) via trap-assisted tunneling when the gate voltage (V) is lower than the specific voltage associated with the trap level. The oxygen vacancies were successfully passivated after the annealing of ZnO in oxygen ambient.

Performance Degradation in Graphene-ZnO Barristors Due to Graphene Edge Contact.

The physical and chemical characteristics of the edge states of graphene have been studied extensively as they affect the electrical properties of graphene significantly. Likewise, the edge states of graphene in contact with semiconductors or transition-metal dichalcogenides (TMDs) are expected to have a strong influence on the electrical properties of the resulting Schottky junction devices. We found that the edge states of graphene form chemical bonds with the ZnO layer, which limits the modulation of the Fermi level at the graphene-semiconductor junction, in a manner similar to Fermi level pinning in silicon devices.