J Nanosci Nanotechnol
February 2016
The electrical characteristics of NAND flash memories with a high-k dielectric layer were simulated by using a full three-dimensional technology computer-aided design simulator. The occurrence rate of the errors in the flash memories increases with increasing program/erase cycles. To verify the word line stress effect, electron density in the floating gate of target cell and non-target cell, the drain current in the channel of non-target cell and depletion region of the non-target cell were simulated as a function of program/erase cycle, for various floating gate thicknesses.
View Article and Find Full Text PDFCdSe/CdS/ZnS core-shell-shell quantum dots (QDs) were synthesized by using a solution process. High-resolution transmission electron microscopy images and energy dispersive spectroscopy profiles confirmed that stoichiometric CdSe/CdS/ZnS core-shell-shell QDs were formed. Ultraviolet-visible absorption and photoluminescence (PL) spectra of CdSe/CdS/ZnS core-shell-shell QDs showed the dominant excitonic transitions from the ground electronic subband to the ground hole subband (1S(e)-1S(3/2)(h)).
View Article and Find Full Text PDFNAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length.
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