Room-temperature spin injection across a chiral perovskite/III-V interface.

Spin accumulation in semiconductor structures at room temperature and without magnetic fields is key to enable a broader range of optoelectronic functionality. Current efforts are limited owing to inherent inefficiencies associated with spin injection across semiconductor interfaces. Here we demonstrate spin injection across chiral halide perovskite/III-V interfaces achieving spin accumulation in a standard semiconductor III-V (AlGa)InP multiple quantum well light-emitting diode.

Quantitative order-parameter measurement in lattice-mismatched AlInP using precession electron diffraction.

Precession electron diffraction (PED) was used to measure the long-range order parameter in lattice-mismatched AlInP epitaxial films under investigation for solid-state-lighting applications. Both double- and single-variant films grown at 620, 650 and 680 °C were analysed in TEM cross-section. PED patterns were acquired in selected-area-diffraction mode through external microscope control using serial acquisition, which allows inline image processing.

Tailoring Heterovalent Interface Formation with Light.

Integrating different semiconductor materials into an epitaxial device structure offers additional degrees of freedom to select for optimal material properties in each layer. However, interfaces between materials with different valences (i.e.

Ultra-low threshold polariton condensation.

We demonstrate the condensation of microcavity polaritons with a very sharp threshold occurring at a two orders of magnitude pump intensity lower than previous demonstrations of condensation. The long cavity lifetime and trapping and pumping geometries are crucial to the realization of this low threshold. Polariton condensation, or "polariton lasing" has long been proposed as a promising source of coherent light at a lower threshold than traditional lasing, and these results indicate some considerations for optimizing designs for lower thresholds.

Suppression of compensating native defect formation during semiconductor processing via excess carriers.

In many semiconductors, compensating defects set doping limits, decrease carrier mobility, and reduce minority carrier lifetime thus limiting their utility in devices. Native defects are often responsible. Suppressing the concentrations of compensating defects during processing close to thermal equilibrium is difficult because formation enthalpies are lowered as the Fermi level moves towards the majority band edge.