Memcapacitor Crossbar Array with Charge Trap NAND Flash Structure for Neuromorphic Computing.

The progress of artificial intelligence and the development of large-scale neural networks have significantly increased computational costs and energy consumption. To address these challenges, researchers are exploring low-power neural network implementation approaches and neuromorphic computing systems are being highlighted as potential candidates. Specifically, the development of high-density and reliable synaptic devices, which are the key elements of neuromorphic systems, is of particular interest.

Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfO-based metal-ferroelectric-insulator-semiconductor stack.

Ferroelectric tunnel junction (FTJ) has been considered as a promising candidate for next-generation memory devices due to its non-destructive and low power operations. In this article, we demonstrate the interlayer (IL) engineering in the FTJs to boost device performances. Through the analysis on the material and electrical characteristics of the fabricated FTJs with engineered IL stacks, it is clearly found that the insertion of an AlOlayer between the SiOinsulator and the pure-HfOFE improves the read disturbance (2 = 2.

A novel physical unclonable function (PUF) using 16 × 16 pure-HfOferroelectric tunnel junction array for security applications.

As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits.

Low-Latency Spiking Neural Networks Using Pre-Charged Membrane Potential and Delayed Evaluation.

Spiking neural networks (SNNs) have attracted many researchers' interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron.

Improvement in Self-Heating Characteristic by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application.

In this study, we propose an omega-shaped-gate nanowire field effect transistor (ONWFET) with a silicon-on-sapphire (SOS) substrate. In order to investigate improvements in the self-heating characteristic with the use of a SOS substrate, the lattice temperature is examined using a Synopsys Sentaurus 3D Technology computer-aided design (TCAD) simulator with the results compared to those with a silicon-on-insulator (SOI) substrate. To validate the proposed structure with the SOS substrate, the locations of hot spots and heat dissipation paths (heat sinks) depending on the substrate materials are also analyzed.

Electrical and Thermal Performances of Omega-Shaped-Gate Nanowire Field Effect Transistors for Low Power Operation.

In this paper, we proposed Omega-Shaped-Gate Nanowire Field Effect Transistor (ONWFET) with different gate coverage ratio (GCR). In order to investigate electrical and self-heating characteristics of the proposed devices, on-current, off-current, subthreshold swing (SS), and operating temperature were examined by using 3D TCAD simulator and compared with nanowire MOSFET (NW-MOSFET). As a result, a possibility of reducing off-current and operating temperature was demonstrated by using the ONWFET with 40% GCR.

Investigation on Ambipolar Current Suppression Using a Stacked Gate in an L-shaped Tunnel Field-Effect Transistor.

L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel. However, L-shaped TFET is disadvantageous for low-power applications because of increased off-current due to the large ambipolar current. In this paper, a stacked gate L-shaped TFET is proposed for suppression of ambipolar current.