Effect of Mask Geometry Variation on Plasma Etching Profiles.

It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, "there's plenty of room at the top". The fabrication of vertical, three-dimensional features as enablers of these advanced technologies in semiconductor devices is commonly achieved using plasma etching. Of the available plasma chemistries, SF/O is one of the most frequently applied.