Charge-trap synaptic device with polycrystalline silicon channel for low power in-memory computing.

Processing-in-memory (PIM) is gaining tremendous research and commercial interest because of its potential to replace the von Neumann bottleneck in current computing architectures. In this study, we implemented a PIM hardware architecture (circuit) based on the charge-trap flash (CTF) as a synaptic device. The PIM circuit with a CT memory performed exceedingly well by reducing the inference energy in the synapse array.

On-Chip Annealing Using Embedded Micro-Heater for Highly Sensitive and Selective Gas Detection.

The demand for gas sensing systems that enable fast and precise gas recognition is growing rapidly. However, substantial challenges arise from the complex fabrication process of sensor arrays, time-consuming data transmission to an external processor, and high energy consumption in multi-stage data processing. In this study, a gas sensing system using on-chip annealing for fast and power-efficient gas detection is proposed.

Simulation of a randomly percolated CNT network for an improved analog physical unclonable function.

Carbon nanotube networks (CNTs)-based devices are well suited for the physically unclonable function (PUF) due to the inherent randomness of the CNT network, but CNT networks can vary significantly during manufacturing due to various controllable process conditions, which have a significant impact on PUF performance. Therefore, optimization of process conditions is essential to have a PUF with excellent performance. However, because it is time-consuming and costly to fabricate directly under various conditions, we implement randomly formed CNT network using simulation and confirm the variable correlation of the CNT network optimized for PUF performance.

Gate Capacitance Coupling of Double-Gate Carbon Nanotube Network Transistors.

Carbon nanotube (CNT) network channels constructed using a high-purity CNT solution for use in CNT thin-film transistors have the advantages of the possibility of requiring a low-temperature process and needing no special equipment. However, there are empty spaces between individual CNTs, resulting in unexpected effects. In this study, double-gate (DG) CNT network transistors were fabricated and measured in four different configurations to observe the capacitive coupling effects between the top gate (TG) and bottom gate (BG) in the DG structure.

Wafer-scale striped network transistors based on purified semiconducting carbon nanotubes for commercialization.

Highly purified and solution-processed semiconducting carbon nanotubes (s-CNTs) have developed rapidly over the past several decades and are near-commercially available materials that can replace silicon due to its large-area substrate deposition and room-temperature processing compatibility. However, the more s-CNTs are purified, the better their electrical performance, but considerable effort and long centrifugation time are required, which can limit commercialization due to high manufacturing costs. In this work, we therefore fabricated 'striped' CNT network transistor across industry-standard 8 inch wafers.

Short-Term Memory Characteristics of IGZO-Based Three-Terminal Devices.

A three-terminal synaptic transistor enables more accurate controllability over the conductance compared with traditional two-terminal synaptic devices for the synaptic devices in hardware-oriented neuromorphic systems. In this work, we fabricated IGZO-based three-terminal devices comprising HfAlO and CeO layers to demonstrate the synaptic operations. The chemical compositions and thicknesses of the devices were verified by transmission electron microscopy and energy dispersive spectroscopy in cooperation.

Investigation of Deep Spiking Neural Networks Utilizing Gated Schottky Diode as Synaptic Devices.

Deep learning produces a remarkable performance in various applications such as image classification and speech recognition. However, state-of-the-art deep neural networks require a large number of weights and enormous computation power, which results in a bottleneck of efficiency for edge-device applications. To resolve these problems, deep spiking neural networks (DSNNs) have been proposed, given the specialized synapse and neuron hardware.

Effect of Post-Annealing on Barrier Modulations in Pd/IGZO/SiO/p-Si Memristors.

In this article, we study the post-annealing effect on the synaptic characteristics in Pd/IGZO/SiO/p-Si memristor devices. The O-H bond in IGZO films affects the switching characteristics that can be controlled by the annealing process. We propose a switching model based on using a native oxide as the Schottky barrier.

Compact SPICE Model of Memristor with Barrier Modulated Considering Short- and Long-Term Memory Characteristics by IGZO Oxygen Content.

This paper introduces a compact SPICE model of a two-terminal memory with a Pd/Ti/IGZO/p-Si structure. In this paper, short- and long-term components are systematically separated and applied in each model. Such separations are conducted by the applied bias and oxygen flow rate (OFR) during indium gallium zinc oxide (IGZO) deposition.

Synergistic improvement of sensing performance in ferroelectric transistor gas sensors using remnant polarization.

Gaseous pollutants, including nitrogen oxides, pose a severe threat to ecosystems and human health; therefore, developing reliable gas-sensing systems to detect them is becoming increasingly important. Among the various options, metal-oxide-based gas sensors have attracted attention due to their capability for real-time monitoring and large response. In particular, in the field of materials science, there has been extensive research into controlling the morphological properties of metal oxides.

Ultrathin ferroic HfO-ZrO superlattice gate stack for advanced transistors.

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO (ref. ), which remains the material of choice to date.

Analysis of Threshold Voltage Shift for Full V/V/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors.

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out.

Proposition of deposition and bias conditions for optimal signal-to-noise-ratio in resistor- and FET-type gas sensors.

In the field of gas sensor studies, most researchers are focusing on improving the response of the sensors to detect a low concentration of gas. However, factors that make a large response, such as abundant or strong adsorption sites, also work as a source of noise, resulting in a trade-off between response and noise. Thus, the response alone cannot fully evaluate the performance of sensors, and the signal-to-noise-ratio (SNR) should additionally be considered to design gas sensors with optimal performance.

On-Chip Training Spiking Neural Networks Using Approximated Backpropagation With Analog Synaptic Devices.

Hardware-based spiking neural networks (SNNs) inspired by a biological nervous system are regarded as an innovative computing system with very low power consumption and massively parallel operation. To train SNNs with supervision, we propose an efficient on-chip training scheme approximating backpropagation algorithm suitable for hardware implementation. We show that the accuracy of the proposed scheme for SNNs is close to that of conventional artificial neural networks (ANNs) by using the stochastic characteristics of neurons.

Pruning for Hardware-Based Deep Spiking Neural Networks Using Gated Schottky Diode as Synaptic Devices.

Deep learning represents state-of-the-art results in various machine learning tasks, but for applications that require real-time inference, the high computational cost of deep neural networks becomes a bottleneck for the efficiency. To overcome the high computational cost of deep neural networks, spiking neural networks (SNN) have been proposed. Herein, we propose a hardware implementation of the SNN with gated Schottky diodes as synaptic devices.

Implementation of Synaptic Device Using Various High- Gate Dielectric Stacks.

We investigate the characteristics of short-term and long-term synaptic plasticity in a Si-based fieldeffect transistor (FET)-type memory device. An Al₂O₃/HfO₂/Si₃N₄/SiO₂ gate dielectric stack is used to realize short-term and long-term plasticity (STP/LTP). Si₃N₄ and HfO₂ layers are designed to charge trap layer for synaptic device.

Effect of Word-Line Bias on Linearity of Multi-Level Conductance Steps for Multi-Layer Neural Networks Based on NAND Flash Cells.

NAND flash memory which is mature technology has great advantage in high density and great storage capacity per chip because cells are connected in series between a bit-line and a source-line. Therefore, NAND flash cell can be used as a synaptic device which is very useful for a high-density synaptic array. In this paper, the effect of the word-line bias on the linearity of multi-level conductance steps of the NAND flash cell is investigated.

Humidity-Sensitive Field Effect Transistor with In₂O₃ Nanoparticles as a Sensing Layer.

In this work, we investigate the humidity-sensing performance on a humidity-sensitive p-channel field effect transistor (FET) having a floating-gate (FG) and a control-gate (CG) placing horizontally each other. A sensing layer is formed onto a part of the CG and the O/N/O stack over the FG by inkjet-printing process. The printed ink is composed of indium oxide (In₂O₃.

Gated Schottky Diode-Type Synaptic Device with a Field-Plate Structure to Reduce the Forward Current.

A gated Schottky diode with a field-plate structure is proposed and investigated as a new low-power synaptic device to suppress the forward current of the Schottky diode. In a hardware-based neural network, unwanted forward current can flow through gated Schottky diode-type synaptic devices during integration operations, possibly causing a malfunction of the neural network and increasing the power consumption. By adopting a field-plate structure, a virtual junction to suppress the forward current of the Schottky diode is formed in the poly-Si active layer.

Emerging memory technologies for neuromorphic computing.

In this paper, we reviewed the recent trends on neuromorphic computing using emerging memory technologies. Two representative learning algorithms used to implement a hardware-based neural network are described as a bio-inspired learning algorithm and software-based learning algorithm, in particular back-propagation. The requirements of the synaptic device to apply each algorithm were analyzed.