Engineering High- k/SiGe Interface with ALD Oxide for Selective GeO Reduction.

Suppression of electronic defects induced by GeO at the high- k gate oxide/SiGe interface is critical for implementation of high-mobility SiGe channels in complementary metal-oxide-semiconductor (CMOS) technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO -rich interlayer on SiGe. Experimental studies in the literature indicate a better interface formation with AlO in contrast to HfO on SiGe; however, the mechanism behind this is not well understood.