Publications by authors named "Jingtong Hu"

Article Synopsis
  • - DNNs are transitioning from simple models (single-modality, single-task) to more complex ones (multi-modality, multi-task), which require advanced hardware solutions to handle their varying layers and complex dependencies.
  • - Heterogeneous systems are being developed, integrating different accelerators to reduce latency, with FPGAs being a key component due to their high density and configurability for machine-learning tasks.
  • - The authors introduce CHEF, a framework that efficiently implements these complex models on heterogeneous FPGA clusters, featuring two main approaches (CHEF-A2F and CHEF-M2A) that significantly reduce latency and search times compared to previous methods.
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Background And Purpose: Ultrasonographic optic nerve sheath (ONS) diameter is a noninvasive intracranial pressure (ICP) surrogate. ICP is monitored invasively in specialized intensive care units. Noninvasive ICP monitoring is important in less specialized settings.

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Supervised deep learning needs a large amount of labeled data to achieve high performance. However, in medical imaging analysis, each site may only have a limited amount of data and labels, which makes learning ineffective. Federated learning (FL) can learn a shared model from decentralized data.

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The 55th Design Automation Conference (DAC) held its first System Design Contest (SDC) in 2018. SDC'18 features a lower power object detection challenge (LPODC) on designing and implementing novel algorithms based object detection in images taken from unmanned aerial vehicles (UAV). The dataset includes 95 categories and 150k images, and the hardware platforms include Nvidia's TX2 and Xilinx's PYNQ Z1.

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Racetrack memory (RM) has sparked enormous interest thanks to its outstanding potential for low-power, high-density and high-speed data storage. However, since it requires bi-directional domain wall (DW) shifting process for outputting data, the mainstream stripe-shaped concept certainly suffers from the data overflow issue. This geometrical restriction leads to increasing complexity of peripheral circuits or programming as well as undesirable reliability issue.

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