Development of Self-Aligned Top-Gate Transistor Arrays on Wafer-Scale Two-Dimensional Semiconductor.

Two-dimensional semiconductor materials (2DSM) effectively mitigate the short-channel effect due to their atomic thickness, offering significant advantages over traditional silicon-based materials, particularly in short channel length. In manufacturing 2DSM top-gate field-effect transistors (TG-FETs), simultaneous miniaturization of the gate and channel can only be achieved through a self-alignment process, enabling high-density integration of short-channel FETs. However, current self-aligned FETs based on 2DSM face challenges in attaining wafer-scale integration due to manufacturing process limitations.