CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs).

Correlation between PD-L1 expression status and efficacy of immunotherapy as second-line or later-line therapy in advanced non-small cell lung cancer patients.

Objective: The objective of this study is to evaluate the correlation between tumor proportionality scores (TPS) and the effectiveness of immune checkpoint inhibitors (ICIs) as the second or subsequent line therapies for individuals who received diagnoses of advanced non-small cell lung cancer (NSCLC).

Methods: The retrospective analysis was conducted on the medical records of a total of 143 patients who received diagnoses of stage IIIB/IV NSCLC and were admitted to our hospital from the beginning of 2019 to the end of September 2022. The follow-up period ended on 01 January 2023.

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale.

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: "self-alignment of gate and channel" and "precise gate length control".

The linear impact of visual working memory load on visual awareness: Evidence from motion-induced blindness.

Despite the close relationship between visual working memory (VWM) and visual awareness, the question of how these two constructs interact with each other is still under debate. The current study aimed to further address this issue by investigating whether and how visual awareness is influenced by VWM load. In Experiment 1, participants were asked to perform a motion-induced blindness (MIB) task while simultaneously memorizing different numbers of items in VWM.

Colorimetric/photothermal dual-mode sensing detection of ascorbic acid based on a Ag[i] ion/3,3',5,5'-tetramethylbenzidine (TMB) system.

In this work, a novel strategy of colorimetric and photothermal dual-mode sensing determination of ascorbic acid (AA) based on a Ag/3,3',5,5'-tetramethylbenzidine (TMB) system was developed. In this sensing system, Ag could oxidize TMB with a distinct color change from colorless to blue color, strong absorbance at 652 nm and a photothermal effect under 808 nm laser irradiation due to the formation of oxidized TMB (oxTMB). When AA was present, oxTMB was reduced accompanied by a change from blue to colorless, and a decrease in absorption peak intensity and the photothermal effect.

Reduced Dislocation of GaAs Layer Grown on Ge-Buffered Si (001) Substrate Using Dislocation Filter Layers for an O-Band InAs/GaAs Quantum Dot Narrow-Ridge Laser.

The development of the low dislocation density of the Si-based GaAs buffer is considered the key technical route for realizing InAs/GaAs quantum dot lasers for photonic integrated circuits. To prepare the high-quality GaAs layer on the Si substrate, we employed an engineered Ge-buffer on Si, used thermal cycle annealing, and introduced filtering layers, e.g.

Monolithic Integration of O-Band InAs Quantum Dot Lasers with Engineered GaAs Virtual Substrate Based on Silicon.

The realization of high-performance Si-based III-V quantum-dot (QD) lasers has long attracted extensive interest in optoelectronic circuits. This manuscript presents InAs/GaAs QD lasers integrated on an advanced GaAs virtual substrate. The GaAs layer was originally grown on Ge as another virtual substrate on Si wafer.

Research on the Comprehensive Evaluation Method for the Automatic Recognition of Raman Spectrum under Multidimensional Constraint.

Raman spectrum contains abundant substance information with fingerprint characteristics. However, due to the huge variety of substances and their complex characteristic information, it is difficult to recognize the Raman spectrum accurately. Starting from dimensions like the Raman shift, the relative peak intensity, and the overall hit ratio of characteristic peaks, we extracted and recognized the characteristics in the Raman spectrum and analyzed these characteristics from local and global perspectives and then proposed a comprehensive evaluation method for the recognition of Raman spectrum on the basis of the data fusion of the recognition results under multidimensional constraint.

Enhancement of InSe Field-Effect-Transistor Performance against Degradation of InSe Film in Air Environment.

The degradation of InSe film and its impact on field effect transistors are investigated. After the exposure to atmospheric environment, 2D InSe flakes produce irreversible degradation that cannot be stopped by the passivation layer of h-BN, causing a rapid decrease for InSe FETs performance, which is attributed to the large number of traps formed by the oxidation of 2D InSe and adsorption to impurities. The residual photoresist in lithography can cause unwanted doping to the material and reduce the performance of the device.

Strain Modulation of Selectively and/or Globally Grown Ge Layers.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 10 cm.

Investigation of the Heteroepitaxial Process Optimization of Ge Layers on Si (001) by RPCVD.

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski-Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides.

State of the Art and Future Perspectives in Advanced CMOS Technology.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology.

Source information is inherently linked to working memory representation for auditory but not for visual stimuli.

Failing to remember the source of retrievable information is known as source amnesia. This phenomenon has been extensively investigated in long-term memory but rarely in working memory, as we share the intuition that the source information of an item that we have encountered in the immediate past is always available. However, a recent study (Chen, Carlson, & Wyble, 2018) challenged this common sense by showing the source amnesia for simple visual stimuli (e.

Miniaturization of CMOS.

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy.

Does attribute amnesia occur with the presentation of complex, meaningful stimuli? The answer is, "it depends".

Attribute amnesia (AA) is a recently reported phenomenon whereby participants are unable to report a salient attribute of a stimulus (e.g., the color or identity of a target letter) on which their attention has just been focused during a prior task.

Near-ideal subthreshold swing MoS back-gate transistors with an optimized ultrathin HfO dielectric layer.

In this paper, a near-ideal subthreshold swing MoS back-gate transistor with an optimized ultrathin HfO dielectric layer is reported with detailed physical and electrical characteristics analyses. Ultrathin (10 nm) HfO films created by atomic-layer deposition (ALD) at a low temperature with rapid-thermal annealing (RTA) at different temperatures from 200 °C to 800 °C have a great effect on the electrical characteristics, such as the subthreshold swing (SS), on-to-off current (I /I ) ratio, etc, of the MoS devices. Physical examinations are performed, including x-ray diffraction, atomic force microscopy, and electrical experiments of metal-oxide-semiconductor capacitance-voltage.

Inverted process for graphene integrated circuits fabrication.

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer.