Publications by authors named "James C Ellenbogen"

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine.

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A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade.

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We investigate the interaction of a carbon nanotube with a graphite substrate, using an interlayer potential that explicitly treats the registry dependence of the interaction. The carbon-carbon bond lengths in nanotubes differ slightly from those in flat graphite, so that the naively commensurate angular orientations for the tube with respect to the substrate lattice are destroyed. The interaction of a one-dimensional tube with a two-dimensional substrate then leads to an unusual registry phenomenon not visible in standard layer-on-layer growth: the system develops favorable orientations which clearly are incommensurate.

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Simulations were performed to assess the prospective performance of a 16 Kbit nanowire-based electronic nanomemory system. Commercial off-the-shelf microcomputer system modeling software was applied to evaluate the operation of an ultra-dense storage array. This array consists of demonstrated experimental non-volatile nanowire diode switches, plus encoder-decoder structures consisting of demonstrated experimental nanowire-based nanotransistors, with nanowire interconnects among all the switching devices.

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