Multiple double cross-section transmission electron microscope sample preparation of specific sub-10 nm diameter Si nanowire devices.

The ability to prepare multiple cross-section transmission electron microscope (XTEM) samples from one XTEM sample of specific sub-10 nm features was demonstrated. Sub-10 nm diameter Si nanowire (NW) devices were initially cross-sectioned using a dual-beam focused ion beam system in a direction running parallel to the device channel. From this XTEM sample, both low- and high-resolution transmission electron microscope (TEM) images were obtained from six separate, specific site Si NW devices.

The association between intraoperative electroencephalogram-based measures and pain severity in the post-anaesthesia care unit.

This observational study aimed to identify simple electroencephalogram indices of inadequate intraoperative opioid-mediated nociceptive blockade and to compare these indices with routinely used clinical predictors of severe postoperative pain in adults. Intraoperative trend and waveform data (electrocardiogram, pulse oximetry and electroencephalogram) were collected, pain intensity in the post-anaesthesia care unit was quantified using an 11-point Verbal Rating Score, and opioid administration was recorded. Using the initial post-anaesthesia care unit Verbal Rating Score as the primary endpoint, the relationship between five possible explanatory variables--surgery type, depth of volatile anaesthesia (minimum alveolar concentration), electroencephalogram signs (state entropy, spindle-like activity and delta-band power) and estimated end-of-operation effect-site morphine concentrations--was examined.

Measurement of carrier mobility in silicon nanowires.

We report the first direct capacitance measurements of silicon nanowires (SiNWs) and the consequent determination of field carrier mobilities in undoped-channel SiNW field-effect transistors (FETs) at room temperature. We employ a two-FET method for accurate extraction of the intrinsic channel resistance and intrinsic channel capacitance of the SiNWs. The devices used in this study were fabricated using a top-down method to create SiNW FETs with up to 1000 wires in parallel for increasing the raw capacitance while maintaining excellent control on device dimensions and series resistance.