Dielectrophoretic alignment of carbon nanotubes: theory, applications, and future.

Carbon nanotubes (CNTs) are nominated to be the successor of several semiconductors and metals due to their unique physical and chemical properties. It has been concerning that the anisotropic and low controllability of CNTs impedes their adoption in commercial applications. Dielectrophoresis (DEP) is known as the electrokinetics motion of polarizable nanoparticles under the influence of nonuniform electric fields.

Airflow-assisted dielectrophoresis to reduce the resistance mismatch in carbon nanotube-based temperature sensors.

The dielectrophoresis (DEP) method is used to fabricate sensor devices by assembling and aligning carbon nanotubes (CNTs) across electrode structures. The challenges of the method increase as the gap width between the electrodes increases. In this work, a novel DEP setup is proposed to reduce the resistance mismatch in manufacturing carbon nanotube-based sensors.

Optimization of Surfactant Concentration in Carbon Nanotube Solutions for Dielectrophoretic Ceiling Assembly and Alignment: Implications for Transparent Electronics.

Surfactants such as sodium dodecyl sulfate (SDS) are used to improve the dispersity of carbon nanotubes (CNTs) in aqueous solutions. The surfactant concentration in CNT solutions is a critical factor in the dielectrophoretic (DEP) manipulation of CNTs. A high surfactant concentration causes a rapid increase in the solution conductivity, while a low concentration results in undesirably large CNT bundles within the solution.

Assembly of long carbon nanotube bridges across transparent electrodes using novel thickness-controlled dielectrophoresis.

The assembly of carbon nanotubes (CNTs) across planner electrodes using dielectrophoresis (DEP) is one of the standard methods used to fabricate CNT-based devices such as sensors. The medium drag velocity caused by electrokinetic phenomena such as electrothermal and electroosmotic might drive CNTs away from the deposition area. This problem becomes critical at large-scale electrode structures due to the high attenuation of the DEP force.

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications.

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals.

Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique.

The partial charge transfer technique can expand the dynamic range of a CMOS image sensor by synthesizing two types of signal, namely the long and short accumulation time signals. However the short accumulation time signal obtained from partial transfer operation suffers of non-linearity with respect to the incident light. In this paper, an analysis of the non-linearity in partial charge transfer technique has been carried, and the relationship between dynamic range and the non-linearity is studied.