Four-Bits-Per-Cell Operation in an HfO -Based Resistive Switching Device.

The quadruple-level cell technology is demonstrated in an Au/Al O /HfO /TiN resistance switching memory device using the industry-standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self-compliance and gradual set-switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash.