A low-cost concurrent TSV test architecture with lossless test output compression scheme.

As the traditional IC design migrates to three-dimensional integrated circuits (3D-ICs) design, new challenges need to be considered carefully to solve its reliability and yield issues. 3D-ICs using through-silicon-vias (TSVs) can have latent defects such as resistive open and bridge defects, which are caused by the thermal stress during the fabrication process. These latent defects lead to the deterioration of the electrical performance of TSVs caused by an undesired increase in the resistance-capacitance (RC) delay.