A method for the formation of a low-temperature hybrid gate dielectric for high-performance, top-gate ZnO nanowire transistors is reported. The hybrid gate dielectric consists of a self-assembled monolayer (SAM) and an aluminum oxide layer. The thin aluminum oxide layer forms naturally and spontaneously when the aluminum gate electrode is deposited by thermal evaporation onto the SAM-covered ZnO nanowire, and its formation is facilitated by the poor surface wetting of the aluminum on the hydrophobic SAM.
View Article and Find Full Text PDFA fabrication process for the monolithic integration of field-effect transistors based on individual carbon nanotubes and load resistors based on vacuum-evaporated carbon films into fast unipolar logic circuits on glass substrates is reported for the first time. The individual-carbon-nanotube transistors operate with relatively small gate-source and drain-source voltages of 1 V and combine large transconductance (up to 6 μS), large ON/OFF ratio (>10(4)), and short switching delay time constants (12 ns). The thin-film carbon load resistors provide linear current-voltage characteristics and resistances between 300 kΩ and 100 MΩ, depending on the layout of the resistors and the thickness of the vacuum-evaporated carbon films.
View Article and Find Full Text PDFNanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized.
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