Publications by authors named "Hwasuk Cho"

Internet-of-things applications that use machine-learning algorithms have increased the demand for application-specific energy-efficient hardware that can perform both learning and inference tasks to adapt to endpoint users or environmental changes. This paper presents a multilayer-learning neuromorphic system with analog-based multiplier-accumulator (MAC), which can learn training data by stochastic gradient descent algorithm. As a component of the proposed system, a current-mode MAC processor, fabricated in 28-nm CMOS technology, performs both forward and backward processing in a crossbar structure of 500 × 500 6-b transposable SRAM arrays.

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This paper presents an IC implementation of on-chip learning neuromorphic autoencoder unit in a form of rate-based spiking neural network. With a current-mode signaling scheme embedded in a 500 × 500 6b SRAM-based memory, the proposed architecture achieves simultaneous processing of multiplications and accumulations. In addition, a transposable memory read for both forward and backward propagations and a virtual lookup table are also proposed to perform an unsupervised learning of restricted Boltzmann machine.

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This paper presents an amplifier-less and digital-intensive current-to-digital converter for ion-sensitive FET sensors. Capacitance on the input node is utilized as a residue accumulator, and a clocked comparator is followed for quantization. Without any continuous-time feedback circuit, the converter performs a first-order noise shaping of the quantization error.

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