Polarity-Tunable Photocurrent through Band Alignment Engineering in a High-Speed WSe/SnSe Diode with Large Negative Responsivity.

Excellent light-matter interaction and a wide range of thickness-tunable bandgaps in layered vdW materials coupled by the facile fabrication of heterostructures have enabled several avenues for optoelectronic applications. Realization of high photoresponsivity at fast switching speeds is a critical challenge for 2D optoelectronics to enable high-performance photodetection for optical communication. Moving away from conventional type-II heterostructure pn junctions towards a WSe/SnSe type-III configuration, we leverage the steep change in tunneling current along with a light-induced heterointerface band shift to achieve high negative photoresponsivity, while the fast carrier transport under tunneling results in high speed.

All-Electrical High-Sensitivity, Low-Power Dual-Mode Gas Sensing and Recovery with a WSe/MoS pn Heterodiode.

Two-dimensional MoS gas sensors have conventionally relied on a change in field-effect-transistor (FET) channel resistance or in the Schottky contact/pn homojunction barrier. We demonstrate an enhancement in sensitivity (6×) and dynamic response along with a reduction in detection limit (8×) and power (10×) in a gate-tunable type-II WSe(p)/MoS(n) heterodiode gas sensor over an MoS FET on the same flake. Measurements for varying NO concentration, gate bias, and MoS flake thickness, reinforced with first-principles calculations, indicate dual-mode operation due to (i) a series resistance-based exponential change in the high-bias thermionic current (high sensitivity), and (ii) a heterointerface carrier concentration-based linear change in near-zero-bias interlayer recombination current (low power) resulting in sub-100 μW/cm power consumption.

Electrically Tunable Room Temperature Hysteresis Crossover in Underlap MoS Field-Effect Transistors.

Clockwise to anticlockwise hysteresis crossover in current-voltage transfer characteristics of field-effect transistors (FETs) with graphene and MoS channels holds significant promise for nonvolatile memory applications. However, such crossovers have been shown to manifest only at high temperature. In this work, for the first time, we demonstrate room temperature hysteresis crossover in few-layer MoS FETs using a gate-drain underlap design to induce a differential response from traps near the MoS-HfO channel-gate dielectric interface, also referred to as border traps, to applied gate bias.

Accurate Threshold Voltage Reliability Evaluation of Thin AlO Top-Gated Dielectric Black Phosphorous FETs Using Ultrafast Measurement Pulses.

Few-layer black phosphorus (BP) has attracted significant interest in recent years due to electrical and photonic properties that are far superior to those of other two-dimensional layered semiconductors. The study of long term electrical stability and reliability of black phosphorus field effect transistors (BP-FETs) with technologically relevant thin, and device-selective, gate dielectrics, stressed under realistic (closer to operation) bias and measured using state-of-the-art ultrafast reliability characterization techniques, is essential for their qualification and use in different applications. In this work, air-stable BP-FETs with a thin top-gated dielectric (15 nm AlO, SiO equivalent thickness of 5 nm) were fabricated and comprehensively characterized for threshold voltage ( V) instability under negative gate bias stress at various measurement delays ( t), stress biases ( V), temperatures ( T), and stress times ( t) for the first time.

Enhanced stability and performance of few-layer black phosphorus transistors by electron beam irradiation.

Few layer black phosphorus (BP) has recently emerged as a potential graphene analogue due to its high mobility and direct, appreciable, band gap. The fabrication and characterization of field effect transistors (FETs) involves exposure of the channel material to an electron beam (e-beam) in imaging techniques such as transmission electron microscopy (TEM) and scanning electron microscopy (SEM), and fabrication techniques like electron beam lithography (EBL). Despite this, the effect of e-beam irradiation on BP-FET performance has not been studied experimentally.