Publications by authors named "Hideo Arimoto"

We propose a new low VπL, fully-crystalline, accumulation modulator design based on a thin horizontal gate oxide slot fin waveguide, on bonded double Silicon-on-Insulator (SOI). A combination of anisotropic wet etching and the mirrored crystal alignment of the top and bottom SOI layers allows us for the first time to selectively pattern the bottom layer from above. Simulations presented herein show a VπL = 0.

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