Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure.

Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO/SiN Dual-Layer Insulator.

The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO/SiN dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with SiN single-layer insulator are conducted to the simulation works together. The stacked TiO/SiN GaN MOSFET has a maximum on-state current of 743.

Design and Analysis of DC/DC Boost Converter Using Vertical GaN Power Device.

In this study, a high-performance vertical gallium nitride (GaN) power transistor is designed by using two-dimensional technology computer-aided design simulator. The vertical GaN transistor is used to analyze the DC/DC boost converter. The systems requiring high voltages of 1000 V or more, such as electric vehicles, need wide devices to achieve a high breakdown voltage when using conventional power devices.

The Effect of Grain Boundary on Electrical Characteristics in the Source and Drain Regions of Polycrystalline Silicon Based in One Transistor Dynamic Random Access Memory.

In this paper, we present a capacitorless one transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) double gate MOSFET with grain boundaries (GBs). Several studies have been conducted to implement 1T-DRAM using poly-Si. This is because poly-Si has the advantage of low-cost fabrication and can be stacked.

Design of a Capacitorless Dynamic Random Access Memory Based on Junctionless Dual-Gate Field-Effect Transistor with a Silicon-Germanium/Silicon Nanotube.

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with a silicon-germanium (SiGe) and silicon (Si) nanotube structure was designed and investigated by using technology computer-aided design (TCAD) simulations. Utilizing bandgap engineering to make a quantum well in the core-shell structure, the storage pocket is formed by the difference in bandgap energy between SiGe and Si. By applying different voltage conditions at the inner gate and outer gate, excess holes are generated in the storage region by the band-to-band tunneling (BTBT) mechanism.