Low-Power Hardware Implementation of a Support Vector Machine Training and Classification for Neural Seizure Detection.

In this paper, a low power support vector machine (SVM) training, feature extraction, and classification algorithm are hardware implemented in a neural seizure detection application. The training algorithm used is the sequential minimal optimization (SMO) algorithm. The system is implemented on different platforms: such as field programmable gate array (FPGA), Xilinx Virtex-7 and application specific integrated circuit (ASIC) using hardware-calibrated UMC 65 nm CMOS technology.