LRMP: Layer Replication with Mixed Precision for spatial in-memory DNN accelerators.

In-memory computing (IMC) with non-volatile memories (NVMs) has emerged as a promising approach to address the rapidly growing computational demands of Deep Neural Networks (DNNs). Mapping DNN layers spatially onto NVM-based IMC accelerators achieves high degrees of parallelism. However, two challenges that arise in this approach are the highly non-uniform distribution of layer processing times and high area requirements.

Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective.

Deep learning has become ubiquitous, touching daily lives across the globe. Today, traditional computer architectures are stressed to their limits in efficiently executing the growing complexity of data and models. Compute-in-memory (CIM) can potentially play an important role in developing efficient hardware solutions that reduce data movement from compute-unit to memory, known as the von Neumann bottleneck.

Neural Network Training With Asymmetric Crosspoint Elements.

Analog crossbar arrays comprising programmable non-volatile resistors are under intense investigation for acceleration of deep neural network training. However, the ubiquitous asymmetric conductance modulation of practical resistive devices critically degrades the classification performance of networks trained with conventional algorithms. Here we first describe the fundamental reasons behind this incompatibility.

Algorithm for Training Neural Networks on Resistive Device Arrays.

Hardware architectures composed of resistive cross-point device arrays can provide significant power and speed benefits for deep neural network training workloads using stochastic gradient descent (SGD) and backpropagation (BP) algorithm. The training accuracy on this imminent analog hardware, however, strongly depends on the switching characteristics of the cross-point elements. One of the key requirements is that these resistive devices must change conductance in a symmetrical fashion when subjected to positive or negative pulse stimuli.

RAPA-ConvNets: Modified Convolutional Networks for Accelerated Training on Architectures With Analog Arrays.

Analog arrays are a promising emerging hardware technology with the potential to drastically speed up deep learning. Their main advantage is that they employ analog circuitry to compute matrix-vector products in constant time, irrespective of the size of the matrix. However, ConvNets map very unfavorably onto analog arrays when done in a straight-forward manner, because kernel matrices are typically small and the constant time operation needs to be sequentially iterated a large number of times.

Training LSTM Networks With Resistive Cross-Point Devices.

In our previous work we have shown that resistive cross point devices, so called resistive processing unit (RPU) devices, can provide significant power and speed benefits when training deep fully connected networks as well as convolutional neural networks. In this work, we further extend the RPU concept for training recurrent neural networks (RNNs) namely LSTMs. We show that the mapping of recurrent layers is very similar to the mapping of fully connected layers and therefore the RPU concept can potentially provide large acceleration factors for RNNs as well.

Training Deep Convolutional Neural Networks with Resistive Cross-Point Devices.

In a previous work we have detailed the requirements for obtaining maximal deep learning performance benefit by implementing fully connected deep neural networks (DNN) in the form of arrays of resistive devices. Here we extend the concept of Resistive Processing Unit (RPU) devices to convolutional neural networks (CNNs). We show how to map the convolutional layers to fully connected RPU arrays such that the parallelism of the hardware can be fully utilized in all three cycles of the backpropagation algorithm.

High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes.

As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.

End-bonded contacts for carbon nanotube transistors with low, size-independent resistance.

Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes.

Pathway to the piezoelectronic transduction logic device.

The piezoelectronic transistor (PET) has been proposed as a transduction device not subject to the voltage limits of field-effect transistors. The PET transduces voltage to stress, activating a facile insulator-metal transition, thereby achieving multigigahertz switching speeds, as predicted by modeling, at lower power than the comparable generation field effect transistor (FET). Here, the fabrication and measurement of the first physical PET devices are reported, showing both on/off switching and cycling.

Origins and characteristics of the threshold voltage variability of quasiballistic single-walled carbon nanotube field-effect transistors.

Ultrascaled transistors based on single-walled carbon nanotubes are identified as one of the top candidates for future microprocessor chips as they provide significantly better device performance and scaling properties than conventional silicon technologies. From the perspective of the chip performance, the device variability is as important as the device performance for practical applications. This paper presents a systematic investigation on the origins and characteristics of the threshold voltage (VT) variability of scaled quasiballistic nanotube transistors.

Toward high-performance digital logic technology with carbon nanotubes.

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moore's law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling.

Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors.

Carbon nanotubes (CNTs) continue to show strong promise as the channel material for an aggressively scaled, high-performance transistor technology. However, there has been concern regarding the contact resistance (Rc) in CNT field-effect transistors (CNTFETs) limiting the ultimate performance, especially at scaled contact lengths. In this work, the contact resistance in CNTFETs is defined in the context of a high-performance scaled transistor, including how the demonstrated Rc relates to technology targets.

Graphene radio frequency receiver integrated circuit.

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit.

Schottky-to-Ohmic crossover in carbon nanotube transistor contacts.

For carbon nanotube transistors, as for graphene, the electrical contacts are a key factor limiting device performance. We calculate the device characteristics as a function of nanotube diameter and metal work function. Although the on-state current varies continuously, the transfer characteristics reveal a relatively abrupt crossover from Schottky to Ohmic contacts.

High-performance air-stable n-type carbon nanotube transistors with erbium contacts.

So far, realization of reproducible n-type carbon nanotube (CNT) transistors suitable for integrated digital applications has been a difficult task. In this work, hundreds of n-type CNT transistors from three different low work function metals-erbium, lanthanum, and yttrium-are studied and benchmarked against p-type devices with palladium contacts. The crucial role of metal type and deposition conditions is elucidated with respect to overall yield and performance of the n-type devices.

Carbon nanotube complementary wrap-gate transistors.

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs.

Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics.

Single-walled carbon nanotubes have exceptional electronic properties and have been proposed as a replacement for silicon in applications such as low-cost thin-film transistors and high-performance logic devices. However, practical devices will require dense, aligned arrays of electronically pure nanotubes to optimize performance, maximize device packing density and provide sufficient drive current (or power output) for each transistor. Here, we show that aligned arrays of semiconducting carbon nanotubes can be assembled using the Langmuir-Schaefer method.

High-density integration of carbon nanotubes via chemical self-assembly.

Carbon nanotubes have potential in the development of high-speed and power-efficient logic applications. However, for such technologies to be viable, a high density of semiconducting nanotubes must be placed at precise locations on a substrate. Here, we show that ion-exchange chemistry can be used to fabricate arrays of individually positioned carbon nanotubes with a density as high as 1 × 10(9) cm(-2)-two orders of magnitude higher than previous reports.

Evaluation of field-effect mobility and contact resistance of transistors that use solution-processed single-walled carbon nanotubes.

Solution-processed single-walled carbon nanotubes (SWNTs) offer many unique processing advantages over nanotubes grown by the chemical vapor deposition (CVD) method, including capabilities of separating the nanotubes by electronic type and depositing them onto various substrates in the form of ultradensely aligned arrays at low temperature. However, long-channel transistors that use solution-processed SWNTs generally demonstrate inferior device performance, which poses concerns over the feasibility of using these nanotubes in high-performance logic applications. This paper presents the first systematic study of contact resistance, intrinsic field-effect mobility (μ(FE)), and conductivity (σ(m)) of solution-processed SWNTs based on both the transmission line method and the Y function method.

Variability in carbon nanotube transistors: improving device-to-device consistency.

The large amount of hysteresis and threshold voltage variation in carbon nanotube transistors impedes their use in highly integrated digital applications. The origin of this variability is elucidated by employing a top-coated, hydrophobic monolayer to passivate bottom-gated devices. Compared to passivating only the supporting substrate, it is found that covering the nanotube channel proves highly effective and robust at improving device-to-device consistency-hysteresis and threshold voltage variation are reduced by an average of 84 and 53%, respectively.

Sub-10 nm carbon nanotube transistor.

Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/μm) at a low operating voltage of 0.

High-frequency graphene voltage amplifier.

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm.