Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs).

Gate-defined quantum point contacts in a germanium quantum well.

We report an experimental study of quantum point contacts defined in a high-quality strained germanium quantum well with layered electric gates. At a zero magnetic field, we observed quantized conductance plateaus in units of 2/. Bias-spectroscopy measurements reveal that the energy spacing between successive one-dimensional subbands ranges from 1.

Amorphous oxide semiconductor for monolithic 3D DRAM: an enabler or passer-by?

Whether amorphous oxide semiconductor (AOS) is an enabler or pass-by for monolithic 3D DRAM is discussed, with current challenges and future directions proposed in this perspective.

Effective electrical manipulation of a topological antiferromagnet by orbital torques.

The electrical control of the non-trivial topology in Weyl antiferromagnets is of great interest for the development of next-generation spintronic devices. Recent studies suggest that the spin Hall effect can switch the topological antiferromagnetic order. However, the switching efficiency remains relatively low.

Highly Energy-Efficient Spin Current Generation in SrIrO by Manipulating the Octahedral Rotation.

Materials with strong spin-orbit coupling (SOC) have been continuously attracting intensive attention due to their promising application in energy-efficient, high-density, and nonvolatile spintronic devices. Particularly, transition-metal perovskite oxides with strong SOC have been demonstrated to exhibit efficient charge-spin interconversion. In this study, we systematically investigated the impact of epitaxial strain on the spin-orbit torque (SOT) efficiency in the SrIrO(SIO)/NiFe(Py) bilayer.

The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks.

With characteristic size scaling down to the nanoscale range, the confined geometry exacerbates the self-heating effect (SHE) in nanoscale devices. In this paper, the impact of ambient temperature () on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks () increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends.

Interface Investigation on SiGe/Si Multilayer Structures: Influence of Different Epitaxial Process Conditions.

SiGe/Si multilayer is the core structure of the active area of gate-all-around field-effect transistors and semiconductor quantum computing devices. In this paper, high-quality SiGe/Si multilayers have been grown by a reduced-pressure chemical vapor deposition system. The effects of temperature, pressure, interface processing (dichlorosilane (SiHCl, DCS) and hydrogen chloride (HCl)) on improving the transition thickness of SiGe to Si interfaces were investigated.

Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance.

A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high of ∼291 μA/μm and exhibited good short channel effects (SCEs) control.

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale.

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: "self-alignment of gate and channel" and "precise gate length control".

Undoped Strained Ge Quantum Well with Ultrahigh Mobility of Two Million.

We develop a method to fabricate an undoped Ge quantum well (QW) under a 32 nm relaxed SiGe shallow barrier. The bottom barrier contains SiGe (650 °C) and SiGe (800 °C) such that variation of Ge content forms a sharp interface that can suppress the threading dislocation density (TDD) penetrating into the undoped Ge quantum well. The SiGe barrier introduces enough in-plane parallel strain (ε strain -0.

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique.

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% V recovery ratio from HCD.

A Voltage-Modulated Nanostrip Spin-Wave Filter and Spin Logic Device Thereof.

A nanostrip magnonic-crystal waveguide with spatially periodic width modulation can serve as a gigahertz-range spin-wave filter. Compared with the regular constant-width nanostrip, the periodic width modulation creates forbidden bands (band gaps) at the Brillouin zone boundaries due to the spin-wave reflection by the periodic potential owing to the long-range dipolar interactions. Previous works have shown that there is a critical challenge in tuning the band structures of the magnonic-crystal waveguide once it is fabricated.

Reduced Dislocation of GaAs Layer Grown on Ge-Buffered Si (001) Substrate Using Dislocation Filter Layers for an O-Band InAs/GaAs Quantum Dot Narrow-Ridge Laser.

The development of the low dislocation density of the Si-based GaAs buffer is considered the key technical route for realizing InAs/GaAs quantum dot lasers for photonic integrated circuits. To prepare the high-quality GaAs layer on the Si substrate, we employed an engineered Ge-buffer on Si, used thermal cycle annealing, and introduced filtering layers, e.g.

Monolithic Integration of O-Band InAs Quantum Dot Lasers with Engineered GaAs Virtual Substrate Based on Silicon.

The realization of high-performance Si-based III-V quantum-dot (QD) lasers has long attracted extensive interest in optoelectronic circuits. This manuscript presents InAs/GaAs QD lasers integrated on an advanced GaAs virtual substrate. The GaAs layer was originally grown on Ge as another virtual substrate on Si wafer.

Special Issue: Silicon Nanodevices.

In recent years, nanodevices have attracted a large amount of attention due to their low power consumption and fast operation in electronics and photonics, as well as their high sensitivity in sensor applications [...

Dual-Step Selective Homoepitaxy of Ge with Low Defect Density and Modulated Strain Based on Optimized Ge/Si Virtual Substrate.

In this manuscript, a novel dual-step selective epitaxy growth (SEG) of Ge was proposed to significantly decrease the defect density and to create fully strained relaxed Ge on a Si substrate. With the single-step SEG of Ge, the threading defect density (TDD) was successfully decreased from 2.9 × 10 cm in a globally grown Ge layer to 3.

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration.

In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow.

Growth and Strain Modulation of GeSn Alloys for Photonic and Electronic Applications.

GeSn materials have attracted considerable attention for their tunable band structures and high carrier mobilities, which serve well for future photonic and electronic applications. This research presents a novel method to incorporate Sn content as high as 18% into GeSn layers grown at 285-320 °C by using SnCl and GeH precursors. A series of characterizations were performed to study the material quality, strain, surface roughness, and optical properties of GeSn layers.

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon.

Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs).

Review of Si-Based GeSn CVD Growth and Optoelectronic Applications.

GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys.

An Operation Guide of Si-MOS Quantum Dots for Spin Qubits.

In the last 20 years, silicon quantum dots have received considerable attention from academic and industrial communities for research on readout, manipulation, storage, near-neighbor and long-range coupling of spin qubits. In this paper, we introduce how to realize a single spin qubit from Si-MOS quantum dots. First, we introduce the structure of a typical Si-MOS quantum dot and the experimental setup.