Publications by authors named "Giuseppe Iannaccone"

NanoTCAD ViDES (Versatile DEvice Simulator) is an open-source suite of computing codes aimed at assessing the operation and the performance of nanoelectronic devices. It has served the computational nanoelectronic community for almost two decades and it is freely available to researchers around the world in its website (http://vides.nanotcad.

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Van der Waals coupling with different stacking configurations is emerging as a powerful method to tune the optical and electronic properties of atomically thin two-dimensional materials. Here, we investigate 3R-stacked transition-metal dichalcogenides as a possible option for high-performance atomically thin field-effect transistors (FETs). We report that the effective mobility of 3R bilayer WS (WSe) is 65% (50%) higher than that of 2H WS (WSe).

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Article Synopsis
  • Monolayer MoS is recognized for its potential as an n-type semiconductor, but creating controllable p-type MoS is challenging and essential for advanced electronics.
  • This study presents the successful synthesis of NbS-MoS lateral heterostructures using a one-step method, which leads to p-type behavior with a high on/off current ratio of around 10.
  • The research enhances understanding of the band structure in these heterojunctions and offers scalable methods for creating doped transition metal dichalcogenide materials, supporting future nanoelectronics development.
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In this work, the development, analytical characterization and bioactivity of zeolite-thymol composites, obtained using wet, semi-dry and dry processes, were carried out in order to obtain sustainable and powerful antimicrobial additives. FT-IR, XRD, DSC, TGA, SEM and B.E.

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Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks.

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Lateral heterostructures (LH) of monolayer-multilayer regions of the same noble transition metal dichalcogenide, such as platinum diselenide (PtSe), are promising options for the fabrication of efficient two-dimensional field-effect transistors (FETs), by exploiting the dependence of the energy gap on the number of layers and the intrinsically high quality of the heterojunctions. Key for future progress in this direction is understanding the effects of the physics of the lateral interfaces on far-from-equilibrium transport properties. In this work, a multi-scale approach to device simulation, capable to include ab-initio modelling of the interfaces in a computationally efficient way, is presented.

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Paper is the ideal substrate for the development of flexible and environmentally sustainable ubiquitous electronic systems, which, combined with two-dimensional materials, could be exploited in many Internet-of-Things applications, ranging from wearable electronics to smart packaging. Here we report high-performance MoS field-effect transistors on paper fabricated with a "channel array" approach, combining the advantages of two large-area techniques: chemical vapor deposition and inkjet-printing. The first allows the pre-deposition of a pattern of MoS; the second, the printing of dielectric layers, contacts, and connections to complete transistors and circuits fabrication.

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We report room temperature Hall mobility measurements, low temperature magnetoresistance analysis and low-frequency noise characterization of inkjet-printed graphene films on fused quartz and SiO/Si substrates. We found that thermal annealing in vacuum at 450 °C is a necessary step in order to stabilize the Hall voltage across the devices, allowing their electrical characterization. The printed films present a minimum sheet resistance of 23.

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The bandgap dependence on the number of atomic layers of some families of two-dimensional (2D) materials can be exploited to engineer and use lateral heterostructures (LHs) as high-performance field-effect transistors (FETs). This option can provide very good lattice matching as well as high heterointerface quality. More importantly, this bandgap modulation with layer stacking can give rise to steep transitions in the density of states (DOS) of the 2D material that can eventually be used to achieve sub-60 mV/decade subthreshold swing in LH-FETs thanks to an energy-filtering source.

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A well-defined insulating layer is of primary importance in the fabrication of passive ( e.g., capacitors) and active ( e.

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In the version of this Perspective originally published, in the email address for the author Giuseppe Iannaccone, the surname was incorrectly given as "innaconne"; this has now been corrected in all versions of the Perspective. Also, an error in the production process led to Figs. 1, 2 and 3 being of low resolution; these have now been replaced with higher-quality versions.

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New device concepts can increase the functionality of scaled electronic devices, with reconfigurable diodes allowing the design of more compact logic gates being one of the examples. In recent years, there has been significant interest in creating reconfigurable diodes based on ultrathin transition metal dichalcogenide crystals due to their unique combination of gate-tunable charge carriers, high mobility, and sizeable band gap. Thanks to their large surface areas, these devices are constructed under planar geometry and the device characteristics are controlled by electrostatic gating through rather complex two independent local gates or ionic-liquid gating.

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Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability.

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We present an experimental investigation of slow transients in the gate and drain currents of MoS-based transistors. We focus on the measurement of both the gate and drain currents and, from the comparative analysis of the current transients, we conclude that there are at least two independent trapping mechanisms: trapping of charges in the silicon oxide substrate, occurring with time constants of the order of tens of seconds and involving charge motion orthogonal to the MoS sheet, and trapping at the channel surface, which occurs with much longer time constants, in particular when the device is in a vacuum. We observe that the presence of such slow phenomena makes it very difficult to perform reliable low-frequency noise measurements, requiring a stable and repeatable steady-state bias point condition, and may explain the sometimes contradictory results that can be found in the literature about the dependence of the flicker noise power spectral density on gate bias.

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Vertical metal-insulator-graphene (MIG) diodes for radio frequency (RF) power detection are realized using a scalable approach based on graphene grown by chemical vapor deposition and TiO as barrier material. The temperature dependent current flow through the diode can be described by thermionic emission theory taking into account a bias induced barrier lowering at the graphene TiO interface. The diodes show excellent figures of merit for static operation, including high on-current density of up to 28 A cm, high asymmetry of up to 520, strong maximum nonlinearity of up to 15, and large maximum responsivity of up to 26 V, outperforming state-of-the-art metal-insulator-metal and MIG diodes.

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The performance of devices and systems based on two-dimensional material systems depends critically on the quality of the contacts between 2D material and metal. A low contact resistance is an imperative requirement to consider graphene as a candidate material for electronic and optoelectronic devices. Unfortunately, measurements of contact resistance in the literature do not provide a consistent picture, due to limitations of current graphene technology, and to incomplete understanding of influencing factors.

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Two-dimensional (2D) material based FETs are being considered for future technology nodes and high performance logic applications. However, a comprehensive assessment of 2D material based FETs has been lacking for high performance logic applications considering appropriate system level figure-of-merits (FOMs) e.g.

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We present a new approach to the temperature compensation of MEMS Lamé resonators, based on the combined effect of the doping concentration and of the geometry of etch holes on the equivalent temperature coefficients of silicon. To this purpose, we develop and validate an analytical model which describes the effect of etch holes on the temperature stability of Lamé resonators through comparison with experiments available in the literature and finite-element method (FEM) simulations. We show that two interesting regions of the design space for Lamé resonators exist, where a cancellation of the first-order temperature coefficient of the resonance frequency is possible: [100]-oriented silicon with n-doping of 2.

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Exploiting the properties of two-dimensional crystals requires a mass production method able to produce heterostructures of arbitrary complexity on any substrate. Solution processing of graphene allows simple and low-cost techniques such as inkjet printing to be used for device fabrication. However, the available printable formulations are still far from ideal as they are either based on toxic solvents, have low concentration, or require time-consuming and expensive processing.

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In the race towards high-performance ultra-scaled devices, two-dimensional materials offer an alternative paradigm thanks to their atomic thickness suppressing short-channel effects. It is thus urgent to study the most promising candidates in realistic configurations, and here we present detailed multiscale simulations of field-effect transistors based on arsenene and antimonene monolayers as channels. The accuracy of first-principles approaches in describing electronic properties is combined with the efficiency of tight-binding Hamiltonians based on maximally localized Wannier functions to compute the transport properties of the devices.

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Research in graphene-based electronics is recently focusing on devices based on vertical heterostructures of two-dimensional materials. Here we use density functional theory and multiscale simulations to investigate the tunneling properties of single- and double-barrier structures with graphene and few-layer hexagonal boron nitride (h-BN) or hexagonal boron carbon nitride (h-BC2N). We find that tunneling through a single barrier exhibit a weak dependence on energy.

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We investigate the intrinsic performance of vertical and lateral graphene-based heterostructure field-effect transistors, currently considered the most promising options to exploit graphene properties in post-CMOS electronics. We focus on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. Our analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the Non-Equilibrium Green's Function formalism.

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The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements.

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We investigate a vertically-stacked hybrid photodiode consisting of a thin n-type molybdenum disulfide (MoS2) layer transferred onto p-type silicon. The fabrication is scalable as the MoS2 is grown by a controlled and tunable vapor phase sulfurization process. The obtained large-scale p-n heterojunction diodes exhibit notable photoconductivity which can be tuned by modifying the thickness of the MoS2 layer.

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We propose that lateral heterostructures of single-atomic-layer graphene and hexagonal boron-carbon-nitrogen (hBCN) domains, can represent a powerful platform for the fabrication and the technological exploration of real two-dimensional field-effect transistors. Indeed, hBCN domains have an energy bandgap between 1 and 5 eV, and are lattice-matched with graphene; therefore they can be used in the channel of a FET to effectively inhibit charge transport when the transistor needs to be switched off. We show through ab initio and atomistic simulations that a FET with a graphene-hBCN-graphene heterostructure in the channel can exceed the requirements of the International Technology Roadmap for Semiconductors for logic transistors at the 10 and 7 nm technology nodes.

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