Efficient Characterization of Qudit Logical Gates with Gate Set Tomography Using an Error-Free Virtual Z Gate Model.

Gate set tomography (GST) characterizes the process matrix of quantum logic gates, along with measurement and state preparation errors in quantum processors. GST typically requires extensive data collection and significant computational resources for model estimation. We propose a more efficient GST approach for qudits, utilizing the qudit Hadamard and virtual Z gates to construct fiducials while assuming virtual Z gates are error-free.

High coherence and low cross-talk in a tileable 3D integrated superconducting circuit architecture.

We report high qubit coherence as well as low cross-talk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to two-dimensional (2D) lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring nongalvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proof-of-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times = 149(38) μs, pure echoed dephasing times = 189(34) μs, and single-qubit gate fidelities = 99.