Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors.

Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-in-memory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture.

Steep-Slope Transistor with an Imprinted Antiferroelectric Film.

The effect of negative capacitance (NC), which can internally boost the voltage applied to a transistor, has been considered to overcome the fundamental Boltzmann limit of a transistor. To stabilize the NC effect, the dielectric (DE) must be integrated into a heterostructure with a ferroelectric (FE) film. However, in a multidomain hafnia, the charge boosting effect is reduced owing to a lowering of the depolarization field originating from the stray field at each domain, and simultaneously, the operating voltage increases owing to the voltage division at the DE.

Novel Approach to High κ (∼59) and Low EOT (∼3.8 Å) near the Morphotrophic Phase Boundary with AFE/FE (ZrO/HZO) Bilayer Heterostructures and High-Pressure Annealing.

We present herewith a novel approach of equally thick AFE/FE (ZrO/HZO) bilayer stack heterostructure films for achieving an equivalent oxide thickness (EOT) of 4.1 Å with a dielectric constant (κ) of 56 in complementary metal-oxide semiconductor (CMOS) compatible metal-ferroelectric-metal (MFM) capacitors using a high-pressure annealing (HPA) technique. The low EOT and high κ values were achieved by careful optimization of AFE/FE film thicknesses and HPA conditions near the morphotropic phase boundary (MPB) after field cycling effects.