Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory.

Electrical characteristics with various program temperatures () in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the up to 120 °C and the read temperature () at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current () and threshold voltage (). The shift in the E-P-E pattern is successfully decomposed into the charge loss (Δ) component and the poly-Si GB (Δ) component.

Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory.

The instability in threshold voltage () and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. Using TCAD simulation, we aim to identify the main factors influencing the of noncircular cells. The key focus is on the nonuniform trapped electron density in the charge trapping layer (CTL) caused by the change in electric field between the circular region and the spike region.

FeS-incorporated 3D PCL scaffold improves new bone formation and neovascularization in a rat calvarial defect model.

199Three-dimensional (3D) scaffolds composed of various biomaterials, including metals, ceramics, and synthetic polymers, have been widely used to regenerate bone defects. However, these materials possess clear downsides, which prevent bone regeneration. Therefore, composite scaffolds have been developed to compensate these disadvantages and achieve synergetic effects.

Fabrication and Characterization of Nanonet-Channel LTPS TFTs Using a Nanosphere-Assisted Patterning Technique.

We present the fabrication and electrical characteristics of nanonet-channel (NET) low-temperature polysilicon channel (LTPS) thin-film transistors (TFTs) using a nanosphere-assisted patterning (NAP) technique. The NAP technique is introduced to form a nanonet-channel instead of the electron beam lithography (EBL) or conventional photolithography method. The size and space of the holes in the nanonet structure are well controlled by oxygen plasma treatment and a metal lift-off process.

An Optimal Cure Process to Minimize Residual Void and Optical Birefringence for a LED Silicone Encapsulant.

Silicone resin has recently attracted great attention as a high-power Light Emitting Diode (LED) encapsulant material due to its good thermal stability and optical properties. In general, the abrupt curing reaction of the silicone resin for the LED encapsulant during the curing process induces reduction in the mechanical and optical properties of the LED product due to the generation of residual void and moisture, birefringence, and residual stress in the final formation. In order to prevent such an abrupt curing reaction, the reduction of residual void and birefringence of the silicone resin was observed through experimentation by introducing the multi-step cure processes, while the residual stress was calculated by conducting finite element analysis that coupled the heat of cure reaction and cure shrinkage.