High-aspect-ratio patterns are required for next-generation three-dimensional (3D) semiconductor devices. However, it is challenging to eliminate voids and seams during gap-filling of these high-aspect-ratio patterns, such as deep trenches, especially for nanoscale high-aspect-ratio patterns. In this study, a SiO plasma-enhanced atomic layer deposition process incorporated with ion collision using bias power to the substrate was used for bottom-up trench gap-filling.
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