Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications.

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture.

Implementation of a compact, four-stage, scalable optical interconnect for photonic backplane applications.

We report on the implementation of a dense 512-beam free-space optical interconnect linking four optoelectronic VLSI chips at the backplane level. The system presented maximizes the positioning tolerances of the components by use of slow f-number (f/16) Gaussian beams and oversized apertures. A beam-clustering scheme whereby a 4 x 4 array of beams is transmitted by each minilens is used to provide a high channel density.