A dual mode self-test for a stand alone AES core.

Advanced Encryption Standard (AES) is the most secured ciphertext algorithm that is unbreakable in a software platform's reasonable time. AES has been proved to be the most robust symmetric encryption algorithm declared by the USA Government. Its hardware implementation offers much higher speed and physical security than that of its software implementation.

Design of a BIST implemented AES crypto-processor ASIC.

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms.

Area efficient camouflaging technique for securing IC reverse engineering.

Reverse engineering is a burning issue in Integrated Circuit (IC) design and manufacturing. In the semiconductor industry, it results in a revenue loss of billions of dollars every year. In this work, an area efficient, high-performance IC camouflaging technique is proposed at the physical design level to combat the integrated circuit's reverse engineering.

An approach to increase the power output of Karnafuli Hydroelectric Power Station: A step to sustainable development in Bangladesh's energy sector.

Renewable energy has become the most prominent source of energy to reduce carbon emissions around the globe. Undoubtedly, hydro energy is very much clean energy among other sources. In Bangladesh, hydro energy is available only in a specific southern area contributing several hundred megawatts to the national grid.

A Novel Byte-Substitution Architecture for the AES Cryptosystem.

The performance of Advanced Encryption Standard (AES) mainly depends on speed, area and power. The S-box represents an important factor that affects the performance of AES on each of these factors. A number of techniques have been presented in the literature, which have attempted to improve the performance of the S-box byte-substitution.