Publications by authors named "F Morisot"

This paper summarizes some of the essential aspects for the fabrication of functional devices from bottom-up silicon nanowires. In a first part, the different ways of exploiting nanowires in functional devices, from single nanowires to large assemblies of nanowires such as nanonets (two-dimensional arrays of randomly oriented nanowires), are briefly reviewed. Subsequently, the main properties of nanowires are discussed followed by those of nanonets that benefit from the large numbers of nanowires involved.

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A randomly oriented nanowire network, also called nanonet (NN), is a nano-microstructure that is easily integrated into devices while retaining the advantages of using nanowires. This combination presents a highly developed surface, which is promising for sensing applications while drastically reducing integration costs compared to single nanowire integration. It now remains to demonstrate its effective sensing in real conditions, its selectivity and its real advantages.

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Field effect transistors (FETs) based on networks of randomly oriented Si nanowires (Si nanonets or Si NNs) were biomodified using Thrombin Binding Aptamer (TBA-15) probe with the final objective to sense thrombin by electrical detection. In this work, the impact of the biomodification on the electrical properties of the Si NN-FETs was studied. First, the results that were obtained for the optimization of the (3-Glycidyloxypropyl)trimethoxysilane (GOPS)-based biofunctionalization process by using UV radiation are reported.

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Two-dimensional randomly oriented nanowire (NW) networks, also called nanonets (NNs), have remarkable advantages including low-cost integration, good reproducibility and high sensitivity, which make them a promising material for electronic devices. With this work, we focus on the study of ZnO NNs as channel materials in field effect transistors (FETs). In our process, ZnO NWs were assembled in NNs by the liquid filtration method and were integrated in transistors, with the bottom-gate configuration, using simple technological steps.

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