Publications by authors named "Eric A Joseph"

With the increasing interest in establishing directional etching methods capable of atomic scale resolution for fabricating highly scaled electronic devices, the need for development and characterization of atomic layer etching processes, or generally etch processes with atomic layer precision, is growing. In this work, a flux-controlled cyclic plasma process is used for etching of SiO and Si at the Angstrom-level. This is based on steady-state Ar plasma, with periodic, precise injection of a fluorocarbon (FC) precursor (CF and CHF) and synchronized, plasma-based Ar ion bombardment [D.

View Article and Find Full Text PDF

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching.

View Article and Find Full Text PDF

Directed self-assembly (DSA) of lamellar phase block-co-polymers (BCPs) can be used to form nanoscale line-space patterns. However, exploiting the potential of this process for circuit relevant patterning continues to be a major challenge. In this work, we propose a way to impart two-dimensional pattern information in graphoepitaxy-based lamellar phase DSA processes by utilizing the interactions of the BCP with the template pattern.

View Article and Find Full Text PDF